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REFACTOR: rename arty35t explicitly #1682

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merged 2 commits into from
Dec 4, 2023
Merged

REFACTOR: rename arty35t explicitly #1682

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e078fcb
REFACTOR: rename arty35t explicitly
T-K-233 Dec 4, 2023
00c4992
FIX: update github CI
T-K-233 Dec 4, 2023
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4 changes: 2 additions & 2 deletions .github/scripts/defaults.sh
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Original file line number Diff line number Diff line change
Expand Up @@ -34,7 +34,7 @@ grouping["group-accels"]="chipyard-mempress chipyard-sha3 chipyard-hwacha chipya
grouping["group-constellation"]="chipyard-constellation"
grouping["group-tracegen"]="tracegen tracegen-boom"
grouping["group-other"]="icenet testchipip constellation rocketchip-amba rocketchip-tlsimple rocketchip-tlwidth rocketchip-tlxbar"
grouping["group-fpga"]="arty arty100t nexysvideo vc707 vcu118"
grouping["group-fpga"]="arty35t arty100t nexysvideo vc707 vcu118"

# key value store to get the build strings
declare -A mapping
Expand Down Expand Up @@ -79,7 +79,7 @@ mapping["rocketchip-tlsimple"]="SUB_PROJECT=rocketchip CONFIG=TLSimpleUnitTestCo
mapping["rocketchip-tlwidth"]="SUB_PROJECT=rocketchip CONFIG=TLWidthUnitTestConfig"
mapping["rocketchip-tlxbar"]="SUB_PROJECT=rocketchip CONFIG=TLXbarUnitTestConfig"

mapping["arty"]="SUB_PROJECT=arty verilog"
mapping["arty35t"]="SUB_PROJECT=arty35t verilog"
mapping["arty100t"]="SUB_PROJECT=arty100t verilog"
mapping["nexysvideo"]="SUB_PROJECT=nexysvideo verilog"
mapping["vc707"]="SUB_PROJECT=vc707 verilog"
Expand Down
6 changes: 3 additions & 3 deletions fpga/Makefile
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Expand Up @@ -72,11 +72,11 @@ ifeq ($(SUB_PROJECT),nexysvideo)
FPGA_BRAND ?= xilinx
endif

ifeq ($(SUB_PROJECT),arty)
ifeq ($(SUB_PROJECT),arty35t)
# TODO: Fix with Arty
SBT_PROJECT ?= fpga_platforms
MODEL ?= ArtyFPGATestHarness
VLOG_MODEL ?= ArtyFPGATestHarness
MODEL ?= Arty35THarness
VLOG_MODEL ?= Arty35THarness
MODEL_PACKAGE ?= chipyard.fpga.arty
CONFIG ?= TinyRocketArtyConfig
CONFIG_PACKAGE ?= chipyard.fpga.arty
Expand Down
8 changes: 4 additions & 4 deletions fpga/src/main/scala/arty/HarnessBinders.scala
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Expand Up @@ -15,19 +15,19 @@ import chipyard.harness.{HarnessBinder}
import chipyard.iobinders._

class WithArtyDebugResetHarnessBinder extends HarnessBinder({
case (th: ArtyFPGATestHarness, port: DebugResetPort) => {
case (th: Arty35THarness, port: DebugResetPort) => {
th.dut_ndreset := port.io // Debug module reset
}
})

class WithArtyJTAGResetHarnessBinder extends HarnessBinder({
case (th: ArtyFPGATestHarness, port: JTAGResetPort) => {
case (th: Arty35THarness, port: JTAGResetPort) => {
port.io := PowerOnResetFPGAOnly(th.clock_32MHz) // JTAG module reset
}
})

class WithArtyJTAGHarnessBinder extends HarnessBinder({
case (th: ArtyFPGATestHarness, port: JTAGPort) => {
case (th: Arty35THarness, port: JTAGPort) => {
val jtag_wire = Wire(new JTAGIO)
jtag_wire.TDO.data := port.io.TDO
jtag_wire.TDO.driven := true.B
Expand Down Expand Up @@ -62,7 +62,7 @@ class WithArtyJTAGHarnessBinder extends HarnessBinder({
})

class WithArtyUARTHarnessBinder extends HarnessBinder({
case (th: ArtyFPGATestHarness, port: UARTPort) => {
case (th: Arty35THarness, port: UARTPort) => {
withClockAndReset(th.clock_32MHz, th.ck_rst) {
IOBUF(th.uart_rxd_out, port.io.txd)
port.io.rxd := IOBUF(th.uart_txd_in)
Expand Down
2 changes: 1 addition & 1 deletion fpga/src/main/scala/arty/TestHarness.scala
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Expand Up @@ -10,7 +10,7 @@ import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell}

import chipyard.harness.{HasHarnessInstantiators}

class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell with HasHarnessInstantiators {
class Arty35THarness(override implicit val p: Parameters) extends ArtyShell with HasHarnessInstantiators {
// Convert harness resets from Bool to Reset type.
val hReset = Wire(Reset())
hReset := ~ck_rst
Expand Down
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