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Update deprecated/unused Chisel APIs #1743

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Jan 19, 2024
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1 change: 0 additions & 1 deletion fpga/src/main/scala/arty100t/HarnessBinders.scala
Original file line number Diff line number Diff line change
@@ -1,7 +1,6 @@
package chipyard.fpga.arty100t

import chisel3._
import chisel3.experimental.{DataMirror, Direction}

import freechips.rocketchip.jtag.{JTAGIO}
import freechips.rocketchip.subsystem.{PeripheryBusKey}
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2 changes: 1 addition & 1 deletion fpga/src/main/scala/vcu118/bringup/IOBinders.scala
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
package chipyard.fpga.vcu118.bringup

import chisel3._
import chisel3.experimental.{IO, DataMirror}
import chisel3.reflect.DataMirror

import freechips.rocketchip.util.{HeterogeneousBag}
import freechips.rocketchip.tilelink.{TLBundle}
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1 change: 0 additions & 1 deletion generators/chipyard/src/main/scala/Subsystem.scala
Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,6 @@
package chipyard

import chisel3._
import chisel3.internal.sourceinfo.{SourceInfo}

import freechips.rocketchip.prci._
import org.chipsalliance.cde.config.{Field, Parameters}
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Original file line number Diff line number Diff line change
@@ -1,7 +1,6 @@
package chipyard.example

import chisel3._
import chisel3.experimental.{Analog, BaseModule, DataMirror, Direction}
import scala.collection.mutable.{ArrayBuffer, LinkedHashMap}

import org.chipsalliance.cde.config.{Field, Parameters}
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Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,8 @@ package chipyard.harness

import chisel3._
import chisel3.util._
import chisel3.experimental.{Analog, BaseModule, DataMirror, Direction}
import chisel3.reflect.DataMirror
import chisel3.experimental.Direction

import org.chipsalliance.cde.config.{Field, Config, Parameters}
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImpLike}
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Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,6 @@ package chipyard.harness

import chisel3._
import chisel3.util._
import chisel3.experimental.{DataMirror, Direction}

import org.chipsalliance.cde.config.{Field, Config, Parameters}
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImpLike}
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