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Invalid Reg width generation leads to bad bounds in generated Verilog #668
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Do you know if any of the tools have problems handling [-1:0]? I thought they'd error out, but seems like they just trim the signal? Just noticed some of my old (functionally verified w/ Xilinx sim) Verilog had a bunch of those -1's... |
I was only looking at outputs, not trying to run it through anything. But I think if [-1:0] is making it to the backend, there's something seriously wrong. |
I agree :\ |
Actually I think this may just be a very simple bug. It looks like
but I think the function should actually be: this is in the file Reg.scala, btw when I make the change, the verilog output I get is:
this solution is also the same as the one employed in RegNext apply methods. Preferably though, Reg's apply would accept a parameter of type Class[Data] for the outType parameter. |
OK, I think I have a good solution that won't break anything:
Does everyone agree that this would be a good solution? |
@JackDavidson Reg(UInt(31)) isn't supposed to assign 31 to anything; it's supposed to create a Reg of the same type as UInt(31) (i.e., UInt(width=5)). It is confusing but well defined. |
@aswaterman alright, fair enough. It looks like this is creating a lot of confusion though. Would it be possible to change the call Reg(UInt(##)) into Reg(UInt) and make Reg(UInt(##)) do what users are expecting? |
The problem is other users expect UInt(31) to be a unsigned integer value of 31. Hence a width of 5. |
TL,DR: There needs to be a width check on signals before generating the final code.
I've found the following circuit generates erroneous Verilog code (I didn't check C++).
It is purposefully BAD Chisel code, but the error should be caught earlier and not end up in Verilog!
Verilog, generates a broken
reg [-1:0] r
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