Fix issue #428: add blackbox sources to argument of icarus-verilog and vcs #429

jiegec · 2021-10-28T13:50:35Z

No description provided.

jiegec · 2021-10-28T15:10:54Z

It seems that the vcs executable is ran under the project root directory.

Update: FIXED now.

ekiwi

Thanks for improving the VCS backend. I am looking forward to your responses.

ekiwi · 2021-10-28T20:04:44Z

src/main/scala/chiseltest/simulator/IcarusSimulator.scala

@@ -7,6 +7,7 @@ import firrtl.options.Dependency
 import firrtl.stage.RunFirrtlTransformAnnotation
 import firrtl.transforms.formal.RemoveVerificationStatements
 import firrtl.{AnnotationSeq, CircuitState}
+import scala.io.Source


What is this import needed for?

ekiwi · 2021-10-28T20:06:52Z

src/main/scala/chiseltest/simulator/IcarusSimulator.scala

@@ -120,7 +121,8 @@ private object IcarusSimulator extends Simulator {
    val simBinary = relTargetDir / "icarus" / topName
    val cmd = List("iverilog") ++ flags ++ List(
      "-o",
-      simBinary.toString(),
+      simBinary.toString()
+    ) ++ BlackBox.blackBoxSources(targetDir) ++ List(


Icarus supports .f files with the -f option. I would prefer if you could use that to keep things more uniform to how the Verilator backend works.

However, it is not working. Let me investigate.

Sadly, the -f option of icarus does not work as expected. The problem is that iverilog expect .f to end with endline. In iverilog 11.0, it silently fails and ignores the file.

oh wow, that sucks

I submitted a PR to firrtl: chipsalliance/firrtl#2405

ekiwi · 2021-10-28T20:07:18Z

src/main/scala/chiseltest/simulator/VcsSimulator.scala

@@ -111,7 +111,8 @@ private object VcsSimulator extends Simulator {
    annos:          AnnotationSeq
  ): Seq[String] = {
    val flags = generateFlags(topName, targetDir, annos)
-    val cmd = List("vcs") ++ flags ++ List("-o", topName, s"$topName.sv", verilogHarness, "vpi.cpp")
+    val cmd = List("vcs") ++ flags ++ List("-o", topName) ++
+      BlackBox.blackBoxSources(targetDir) ++ List(s"$topName.sv", verilogHarness, "vpi.cpp")


Does VCS support .f files with the -f flag? If so, please use that approach to stay as close as possible to what we do in the Verilator backend.

Yes:

-f filename Specify a file that contains a list of source files and compile-time options, including C source files and object files.

ekiwi · 2021-10-28T20:07:38Z

src/main/scala/chiseltest/simulator/BlackBox.scala

+  }
+
+  /** finds paths to blackbox sources */
+  private[chiseltest] def blackBoxSources(targetDir: os.Path): Seq[String] = {


Ideally this function will not be needed (see comments below)

ekiwi · 2021-10-28T20:07:49Z

src/main/scala/chiseltest/simulator/BlackBox.scala

+
+import scala.io.Source
+
+object BlackBox {


please mark this object private

ekiwi · 2021-10-28T20:10:01Z

src/main/scala/chiseltest/simulator/VcsSimulator.scala

@@ -90,7 +90,7 @@ private object VcsSimulator extends Simulator {
      waveformFlags(toplevel.name, state.annotations)

    // the binary we created communicates using our standard IPC interface
-    new IPCSimulatorContext(simCmd, toplevel, VcsSimulator)
+    new IPCSimulatorContext(simCmd, targetDir, toplevel, VcsSimulator)


Could you elaborate on why you need VCS to run in the targetDir instead of the os.pwd? The problem here is that the Verilator simulation will always run in os.pwd and thus I would prefer to keep that the same for all simulators to ensure uniform behavior.

VCS writes vcd file and ucli.key to cwd, and these files should be put under targetDir.

In the current master, VCS backend fails with ./topLevel executable not found.

I think there might be a different solution to this problem. Would you mind putting your second commit in a separate PR? It would be convenient if we could review the two issues separately.

See pr #430.

ekiwi · 2021-10-28T21:23:39Z

To elaborate on the issue of where the simulator is run (i.e. what working directory it uses):

the Verilator backend will always have the current working directory set to be os.pwd since the simulation is linked into the JVM process
for IVerilog and VCS, we could change the current working directory to instead be the target directory
however, if depending on the backend, the working directory changes, then a test relying on plusargs and Verilog black boxes might only work with VCS and not with Verilator or vice versa
that would defeat the purpose of chiseltest which should allow you to write backend agnostic tests

…#428)

jiegec · 2021-10-29T02:04:11Z

Regarding the icarus issue, possible fixes are:

Append EOL to firrtl_black_box_resource_files.f and pass -f firrtl_black_box_resource_files.f to iverilog
Read firrtl_black_box_resource_f line by line and append blackbox sources to command line

ekiwi · 2021-10-29T02:10:49Z

Thanks for debugging. I will try address this upstream.

ekiwi

Let's get this in and then fix the issue in upstream firrtl.

jiegec force-pushed the blackbox-vcs-icarus branch from 5d2cbd9 to 673c2d5 Compare October 28, 2021 13:53

jiegec force-pushed the blackbox-vcs-icarus branch from 673c2d5 to b67172b Compare October 28, 2021 15:22

ekiwi suggested changes Oct 28, 2021

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jiegec force-pushed the blackbox-vcs-icarus branch 2 times, most recently from c0a49d6 to a081428 Compare October 29, 2021 00:51

Read blackbox source list and pass to vcs and icarus-verilog (ucb-bar…

d3b9854

…#428)

jiegec force-pushed the blackbox-vcs-icarus branch from a081428 to d3b9854 Compare October 29, 2021 00:54

ekiwi added this to the 0.5.0 milestone Oct 29, 2021

ekiwi approved these changes Nov 1, 2021

View reviewed changes

ekiwi merged commit 6ac325f into ucb-bar:master Nov 1, 2021

ekiwi mentioned this pull request Nov 4, 2021

BlackBoxSourceHelper: ensure trailing newline in .f file chipsalliance/firrtl#2405

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Fix issue #428: add blackbox sources to argument of icarus-verilog and vcs #429

Fix issue #428: add blackbox sources to argument of icarus-verilog and vcs #429

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Fix issue #428: add blackbox sources to argument of icarus-verilog and vcs #429

Fix issue #428: add blackbox sources to argument of icarus-verilog and vcs #429

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