Merge pull request #2613 from chipsalliance/maintenance-mode

Maintenance mode

.github/PULL_REQUEST_TEMPLATE.md

@@ -1,3 +1,11 @@
+<!--
+
+********** NOTICE **********
+
+This repository is only accepting bug fixes
+
+-->
+
 ### Contributor Checklist
 
 - [ ] Did you add Scaladoc to every public function/method?
@@ -44,7 +52,7 @@ Text from here to the end of the body will be considered for inclusion in the re
 
 ### Reviewer Checklist (only modified by reviewer)
 - [ ] Did you add the appropriate labels?
-- [ ] Did you mark the proper milestone (1.2.x, 1.3.0, 1.4.0) ?
+- [ ] Did you mark the proper milestone (1.6.x, 1.5.x) ?
 - [ ] Did you review?
 - [ ] Did you check whether all relevant Contributor checkboxes have been checked?
 - [ ] Did you mark as `Please Merge`?

.github/workflows/test.yml

@@ -5,6 +5,7 @@ on:
   push:
     branches:
       - master
+      - 1.6.x
       - 1.5.x
       - 1.4.x
       - 1.3.x

.mergify.yml

@@ -8,7 +8,7 @@ pull_request_rules:
   - status-success=all tests passed
   - '#approved-reviews-by>=1'
   - '#changes-requested-reviews-by=0'
-  - base=master
+  - base=1.6.x
   - label="Please Merge"
   - label!="DO NOT MERGE"
   - label!="bp-conflict"
@@ -20,7 +20,7 @@ pull_request_rules:
 - name: backport to 1.5.x
   conditions:
   - merged
-  - base=master
+  - base=1.6.x
   - milestone=1.5.x
   actions:
     backport:
@@ -36,7 +36,7 @@ pull_request_rules:
 - name: backport to 1.4.x, 1.5.x
   conditions:
   - merged
-  - base=master
+  - base=1.6.x
   - milestone=1.4.x
   actions:
     backport:
@@ -53,7 +53,7 @@ pull_request_rules:
 - name: backport to 1.3.x, 1.4.x, 1.5.x
   conditions:
   - merged
-  - base=master
+  - base=1.6.x
   - milestone=1.3.x
   actions:
     backport:

README.md

@@ -1,3 +1,12 @@
+# This project is in maintenance mode
+
+Pull Requests should only be made for bug fixes against versions 1.6 and below (Chisel 3.6 and below).
+
+Please see [CIRCT](https://github.com/llvm/circt) for the next generation FIRRTL compiler.
+Also see [Chisel](https://github.com/chipsalliance/chisel).
+
+---
+
 ![FIRRTL](https://raw.githubusercontent.com/freechipsproject/firrtl/master/doc/images/firrtl_logo.svg?sanitize=true)
 
 ---

build.sbt

@@ -61,7 +61,7 @@ lazy val firrtlSettings = Seq(
 )
 
 lazy val mimaSettings = Seq(
-  mimaPreviousArtifacts := Set()
+  mimaPreviousArtifacts := Set("edu.berkeley.cs" %% "firrtl" % "1.6.0-RC2")
 )
 
 lazy val protobufSettings = Seq(
@@ -152,7 +152,7 @@ lazy val docSettings = Seq(
     "-doc-source-url", {
       val branch =
         if (version.value.endsWith("-SNAPSHOT")) {
-          "master"
+          "1.6.x"
         } else {
           s"v${version.value}"
         }