Microarchitecture implementation of the decoupled vector-fetch accelerator
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a0u seq: Fix VCU deadlock on AMOs
The sreq check should be limited to mcmd.store instead of mcmd.write, as
is consistent elsewhere.  The sreq counter tracks regular stores only,
so a situation may arise with AMOs (for which mcmd.write is true) that
io.mocheck(i).store is deasserted indefinitely due to vu_pending_addr.
Thus, the VCU op is falsely treated as unready and never fires again.

Note that this was not problematic prior to commit 9c9d183 ("Enforce
loads waiting for store acquires finishing") since io.mocheck(i).store
and io.mocheck(i).load would always be asserted for the oldest VCU op,
if no scalar memory ops were pending.
Latest commit c917d5f Jan 3, 2019
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src/main/scala seq: Fix VCU deadlock on AMOs Jan 3, 2019
.gitignore update for fmin->minimun and fmul sign fixes Jun 22, 2017
.gitmodules futher git cleanup Aug 19, 2013
README standardized sbt build Aug 16, 2013
build.sbt sbt: Bump to Scala 2.12.4 Oct 1, 2018


Source repository for the Hwacha vector-thread co-processor.

To use this coprocessor, include this repo as a git submodule and add it as 
to your chip's build.scala as a Project, e.g.
lazy val hwacha = Project("hwacha", file("hwacha"), settings = buildSettings)

Hwacha depends on the Chisel and Hardloat projects, make sure these libraries' 
jars are installed.