Integrate Hwacha for initial public release

.gitmodules

@@ -4,3 +4,13 @@
 [submodule "testchipip"]
 	path = testchipip
 	url = https://github.com/ucb-bar/testchipip.git
+[submodule "hwacha"]
+	path = hwacha
+	url = https://github.com/ucb-bar/hwacha.git
+[submodule "esp-tools"]
+	path = riscv-tools
+	url = https://github.com/ucb-bar/esp-tools.git
+[submodule "torture"]
+	path = torture
+	url = https://github.com/ucb-bar/riscv-torture.git
+	branch = hwacha

Makefrag

@@ -1,6 +1,6 @@
 ROCKETCHIP_DIR=$(base_dir)/rocket-chip
 
-SBT ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -jar $(ROCKETCHIP_DIR)/sbt-launch.jar ++2.12.4
+SBT ?= java -Xmx$(JVM_HEAP_SIZE) -Xss8M -XX:MaxPermSize=256M -jar $(ROCKETCHIP_DIR)/sbt-launch.jar ++2.12.4
 
 lookup_scala_srcs = $(shell find $(1)/ -iname "*.scala" 2> /dev/null)
 
@@ -9,7 +9,7 @@ SCALA_SOURCES=$(foreach pkg,$(PACKAGES),$(call lookup_scala_srcs,$(base_dir)/$(p
 
 ROCKET_CLASSES ?= "$(ROCKETCHIP_DIR)/target/scala-2.12/classes:$(ROCKETCHIP_DIR)/chisel3/target/scala-2.12/*"
 FIRRTL_JAR ?= $(ROCKETCHIP_DIR)/lib/firrtl.jar
-FIRRTL ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -cp $(ROCKET_CLASSES):$(FIRRTL_JAR) firrtl.Driver
+FIRRTL ?= java -Xmx$(JVM_HEAP_SIZE) -Xss8M -XX:MaxPermSize=256M -cp $(ROCKET_CLASSES):$(FIRRTL_JAR) firrtl.Driver
 
 $(FIRRTL_JAR): $(call lookup_scala_srcs, $(ROCKETCHIP_DIR)/firrtl/src/main/scala)
 	$(MAKE) -C $(ROCKETCHIP_DIR)/firrtl SBT="$(SBT)" root_dir=$(ROCKETCHIP_DIR)/firrtl build-scala
@@ -24,47 +24,41 @@ include $(testchip_dir)/Makefrag
 
 CHISEL_ARGS ?=
 
-FIRRTL_FILE=$(build_dir)/$(PROJECT).$(MODEL).$(CONFIG).fir
-ANNO_FILE=$(build_dir)/$(PROJECT).$(MODEL).$(CONFIG).anno.json
-VERILOG_FILE=$(build_dir)/$(PROJECT).$(MODEL).$(CONFIG).v
+FIRRTL_FILE=$(build_dir)/$(long_name).fir
+ANNO_FILE=$(build_dir)/$(long_name).anno.json
+VERILOG_FILE=$(build_dir)/$(long_name).v
 
 $(FIRRTL_FILE) $(ANNO_FILE): $(SCALA_SOURCES) $(bootrom_img) $(FIRRTL_JAR)
 	mkdir -p $(build_dir)
-	cd $(base_dir) && $(SBT) "runMain $(PROJECT).Generator $(CHISEL_ARGS) $(build_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
+	cd $(base_dir) && $(SBT) "runMain $(GENERATOR_PROJECT).Generator $(CHISEL_ARGS) $(build_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
 
 $(VERILOG_FILE): $(FIRRTL_FILE) $(ANNO_FILE) $(FIRRTL_JAR)
 	$(FIRRTL) -i $(FIRRTL_FILE) -o $(VERILOG_FILE) -X verilog -faf $(ANNO_FILE)
 
-regression-tests = \
-	rv64ud-v-fcvt \
-        rv64ud-p-fdiv \
-        rv64ud-v-fadd \
-        rv64uf-v-fadd \
-        rv64um-v-mul \
-        rv64mi-p-breakpoint \
-        rv64uc-v-rvc \
-        rv64ud-v-structural \
-        rv64si-p-wfi \
-        rv64um-v-divw \
-        rv64ua-v-lrsc \
-        rv64ui-v-fence_i \
-        rv64ud-v-fcvt_w \
-        rv64uf-v-fmin \
-        rv64ui-v-sb \
-        rv64ua-v-amomax_d \
-        rv64ud-v-move \
-        rv64ud-v-fclass \
-        rv64ua-v-amoand_d \
-        rv64ua-v-amoxor_d \
-        rv64si-p-sbreak \
-        rv64ud-v-fmadd \
-        rv64uf-v-ldst \
-        rv64um-v-mulh \
-        rv64si-p-dirty
-
 output_dir=$(sim_dir)/output
 
-$(output_dir)/%: $(RISCV)/riscv64-unknown-elf/share/riscv-tests/isa/%
-	mkdir -p $(output_dir)
-	ln -sf $< $@
+# Assembly/Benchmark Testing
+.PRECIOUS: $(output_dir)/%.vpd
+
+$(output_dir)/%.run: $(output_dir)/% $(sim)
+	cd $(sim_dir) && $(exec_sim) +max-cycles=$(timeout_cycles) +permissive-off $< 2> /dev/null 2> $@ && [ $$PIPESTATUS -eq 0 ]
+
+$(output_dir)/%.out: $(output_dir)/% $(sim)
+	cd $(sim_dir) && $(exec_sim) +verbose +max-cycles=$(timeout_cycles) +permissive-off $< $(disasm) $@ && [ $$PIPESTATUS -eq 0 ]
+
+$(output_dir)/%.vcd: $(output_dir)/% $(sim_debug)
+	cd $(sim_dir) && $(exec_sim_debug) +verbose -v$@ +max-cycles=$(timeout_cycles) +permissive-off $< $(disasm) $(patsubst %.vcd,%.out,$@) && [ $$PIPESTATUS -eq 0 ]
+
+$(output_dir)/%.vpd: $(output_dir)/% $(sim_debug)
+	cd $(sim_dir) && $(exec_sim_debug) +verbose +vcdplusfile=$@ +max-cycles=$(timeout_cycles) +permissive-off $< $(disasm) $(patsubst %.vpd,%.out,$@) && [ $$PIPESTATUS -eq 0 ]
+
+$(output_dir)/%.saif: $(output_dir)/% $(sim_debug)
+	cd $(sim_dir) && rm -f $(output_dir)/pipe-$*.vcd && vcd2saif -input $(output_dir)/pipe-$*.vcd -pipe "$(exec_sim_debug) +verbose +vcdfile=$(output_dir)/pipe-$*.vcd +max-cycles=$(bmark_timeout_cycles) +permissive-off $<" -output $@ > $(patsubst %.saif,%.out,$@) 2>&1
+
+run: run-asm-tests run-bmark-tests
+run-debug: run-asm-tests-debug run-bmark-tests-debug
+run-fast: run-asm-tests-fast run-bmark-tests-fast
 
+.PHONY: run-asm-tests run-bmark-tests
+.PHONY: run-asm-tests-debug run-bmark-tests-debug
+.PHONY: run run-debug run-fast

Makefrag-variables

@@ -0,0 +1,37 @@
+PROJECT ?= freechips.rocketchip.system
+MODEL ?= TestHarness
+CONFIG ?= ISCA2016Config
+CFG_PROJECT ?= hwacha
+GENERATOR_PROJECT ?= hwacha
+TB ?= TestDriver
+
+JVM_HEAP_SIZE ?= 16G
+
+long_name = $(PROJECT).$(CONFIG)
+
+rocketchip_vsrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/vsrc
+rocketchip_csrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/csrc
+
+sim_vsrcs = \
+	$(VERILOG_FILE) \
+	$(rocketchip_vsrc_dir)/$(TB).v \
+	$(rocketchip_vsrc_dir)/AsyncResetReg.v \
+	$(rocketchip_vsrc_dir)/plusarg_reader.v \
+	$(rocketchip_vsrc_dir)/SimDTM.v \
+	$(testchip_vsrcs)
+
+sim_csrcs = \
+	$(testchip_csrcs) \
+	$(rocketchip_csrc_dir)/SimDTM.cc
+
+# Assembly/Benchmark Testing
+disasm := 2>
+which_disasm := $(shell which spike-dasm 2> /dev/null)
+ifneq ($(which_disasm),)
+  disasm = 3>&1 1>&2 2>&3 | $(which_disasm) $(DISASM_EXTENSION) >
+endif
+
+timeout_cycles = 10000000
+bmark_timeout_cycles = 100000000
+
+junk += $(output_dir)

README.md

@@ -1,18 +1,30 @@
-# RISC-V Project Template
+# UCB-BAR Hwacha Project Template
 
-This is a starter template for your custom RISC-V project. It will allow you
-to leverage the Chisel HDL and RocketChip SoC generator to produce a
-RISC-V SoC with MMIO-mapped peripherals, DMA, and custom accelerators.
+This is a template for building a rocket-chip with Hwacha.
+
+## Submodules and Subdirectories
+
+The submodules and subdirectories for the project template are organized as
+follows.
+
+ * rocket-chip - contains code for the RocketChip generator, Chisel HCL, and FIRRTL
+ * hwacha - contains code for the Hwacha accelerator
+ * riscv-tools - contains the code for the compiler toolchain that targets Hwacha
+ * testchipip - contains the serial adapter, block device, and associated verilog and C++ code
+ * verisim - directory in which Verilator simulations are compiled and run
+ * vsim - directory in which Synopsys VCS simulations are compiled and run
+ * bootrom - sources for the first-stage bootloader included in the Boot ROM
+ * src/main/scala - scala source files for your project extension go here
 
 ## Getting started
 
 ### Checking out the sources
 
 After cloning this repo, you will need to initialize all of the submodules
 
-    git clone https://github.com/ucb-bar/project-template.git
-    cd project-template
-    git submodule update --init --recursive
+    git clone https://github.com/ucb-bar/hwacha-template.git
+    cd hwacha-template
+    ./scripts/init-submodules
 
 ### Building the tools
 
@@ -38,25 +50,36 @@ An executable called simulator-example-DefaultExampleConfig will be produced.
 You can then use this executable to run any compatible RV64 code. For instance,
 to run one of the riscv-tools assembly tests.
 
-    ./simulator-example-DefaultExampleConfig $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple
+    make output/rv64ui-p-simple.out
 
 If you later create your own project, you can use environment variables to
-build an alternate configuration.
+build an alternate configuration. The different variables are
+
+* PROJECT: The package that contains your test harness class
+* CFG_PROJECT: The package that contains your config class
+* GENERATOR_PROJECT: The package that contains your Generator class
+* MODEL: The class name of your test harness
+* CONFIG: The class name of your config
+
+You can manually override them like this
 
     make PROJECT=yourproject CONFIG=YourConfig
     ./simulator-yourproject-YourConfig ...
 
-## Submodules and Subdirectories
+### Running random tests with torture ###
 
-The submodules and subdirectories for the project template are organized as
-follows.
+RISC-V Torture is included as a submodule and includes the ability to test
+Hwacha.
+You can run a single test like so:
 
- * rocket-chip - contains code for the RocketChip generator and Chisel HDL
- * testchipip - contains the serial adapter, block device, and associated verilog and C++ code
- * verisim - directory in which Verilator simulations are compiled and run
- * vsim - directory in which Synopsys VCS simulations are compiled and run
- * bootrom - sources for the first-stage bootloader included in the Boot ROM
- * src/main/scala - scala source files for your project go here
+    make rgentest R_SIM=../vsim/simv-freechips.rocketchip.chip-ISCA2016Config
+
+You can run a nightly test, which runs for a set amount of time or a set
+number of failures like this:
+
+    make rnight R_SIM=../vsim/simv-freechips.rocketchip.chip-ISCA2016Config OPTIONS="-C config/mem_vec.config -t 5 -m 30"
+
+## THE REMAINDER OF THIS FILE IS COPIED FROM PROJECT-TEMPLATE ##
 
 ## Using the block device
 

build.sbt

@@ -15,6 +15,8 @@ lazy val commonSettings = Seq(
 
 lazy val rocketchip = RootProject(file("rocket-chip"))
 
-lazy val testchipip = project.settings(commonSettings).dependsOn(rocketchip)
+lazy val testchipip = project.settings(commonSettings:_*).dependsOn(rocketchip)
 
-lazy val example = (project in file(".")).settings(commonSettings).dependsOn(testchipip)
+lazy val hwacha = project.settings(commonSettings:_*).dependsOn(rocketchip)
+
+lazy val example = (project in file(".")).settings(commonSettings:_*).dependsOn(testchipip, hwacha)

project/build.properties

@@ -0,0 +1 @@
+sbt.version=1.1.1