Extend ShiftRegisterMem with single-port SRAM implementation #8
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jerryz123
approved these changes
Dec 21, 2022
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I can approve this for now, since the banked implementation looks plausible. Still, the implementation using dual-ported SRAM should be fixed to not rely on SyncReadMem read data being held.
I'm not sure I understand why the expected output is changed. That should be invariant of what the underlying implementation is, right?
FYI chisel-testers/iotesters is EOL, replaced by chiseltest. At some point we will bump Chisel to a point where the tests need to be migrated (if at all).
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You're right the second commit also fixes the dual-port SRAM implementation. So in my opinion by merging this, we'll kill both flies. |
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I'm a bit concerned about the changes to the tests here, but I don't want to delay this further. |
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Add a single-port SRAM implementation of
ShiftRegisterMem. Tests are adjusted accordingly.Furthermore, it is demonstrated that
ShiftRegisterMemwith dual-port SRAM implementation does not have the same behavior across different Chisel3 versions. An issue and feature request related to this topic are opened inside Chisel3 repository (bug & feature request).