Supporting new version of FIRRTL

[sashimi-yzh]

Hi. I have a project using FIRRTL 1.3.2. essent reports the following errors:

line 5:18 mismatched input 'Reset' expecting {'UInt', 'SInt', 'Fixed', 'Clock', 'Analog', '{'}
line 8:45 no viable alternative at input 'undefined@[SRAMTemplate.scala 76:26]'
line 101:18 mismatched input 'Reset' expecting {'UInt', 'SInt', 'Fixed', 'Clock', 'Analog', '{'}
line 104:45 no viable alternative at input 'undefined@[SRAMTemplate.scala 76:26]'
......

For reference, below is the first module in the fir file.

;buildInfoPackage: chisel3, version: 3.3.2, scalaVersion: 2.11.12, sbtVersion: 1.3.10
circuit NutShellSimTop : 
  module SRAMTemplate : 
    input clock : Clock
    input reset : Reset
    output io : {flip r : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {setIdx : UInt<7>}}, flip resp : {data : {tag : UInt<29>, _type : UInt<2>, target : UInt<39>, lateJump : UInt<1>, valid : UInt<1>}[1]}}, flip w : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {setIdx : UInt<7>, data : {tag : UInt<29>, _type : UInt<2>, target : UInt<39>, lateJump : UInt<1>, valid : UInt<1>}}}}}
    
    smem array : UInt<72>[1][128], undefined @[SRAMTemplate.scala 76:26]
    wire resetState : UInt<1>
    resetState <= UInt<1>("h00")
    wire resetSet : UInt
    resetSet <= UInt<1>("h00")
    reg _T : UInt<1>, clock with : (reset => (reset, UInt<1>("h01"))) @[SRAMTemplate.scala 80:30]
    reg _T_1 : UInt<7>, clock with : (reset => (reset, UInt<7>("h00"))) @[Counter.scala 29:33]
    wire _T_2 : UInt<1>
    _T_2 <= UInt<1>("h00")
    when _T : @[Counter.scala 67:17]
      node _T_3 = eq(_T_1, UInt<7>("h07f")) @[Counter.scala 38:24]
      node _T_4 = add(_T_1, UInt<1>("h01")) @[Counter.scala 39:22]
      node _T_5 = tail(_T_4, 1) @[Counter.scala 39:22]
      _T_1 <= _T_5 @[Counter.scala 39:13]
      _T_2 <= _T_3 @[Counter.scala 67:24]
      skip @[Counter.scala 67:17]
    when _T_2 : @[SRAMTemplate.scala 82:24]
      _T <= UInt<1>("h00") @[SRAMTemplate.scala 82:38]
      skip @[SRAMTemplate.scala 82:24]
    resetState <= _T @[SRAMTemplate.scala 84:16]
    resetSet <= _T_1 @[SRAMTemplate.scala 85:14]
    node wen = or(io.w.req.valid, resetState) @[SRAMTemplate.scala 88:52]
    node _T_6 = eq(wen, UInt<1>("h00")) @[SRAMTemplate.scala 89:41]
    node realRen = and(io.r.req.valid, _T_6) @[SRAMTemplate.scala 89:38]
    node setIdx = mux(resetState, resetSet, io.w.req.bits.setIdx) @[SRAMTemplate.scala 91:19]
    wire _T_7 : UInt<72> @[SRAMTemplate.scala 92:47]
    _T_7 <= UInt<1>("h00") @[SRAMTemplate.scala 92:47]
    node _T_8 = cat(io.w.req.bits.data.lateJump, io.w.req.bits.data.valid) @[SRAMTemplate.scala 92:78]
    node _T_9 = cat(io.w.req.bits.data.tag, io.w.req.bits.data._type) @[SRAMTemplate.scala 92:78]
    node _T_10 = cat(_T_9, io.w.req.bits.data.target) @[SRAMTemplate.scala 92:78]
    node _T_11 = cat(_T_10, _T_8) @[SRAMTemplate.scala 92:78]
    node wdataword = mux(resetState, _T_7, _T_11) @[SRAMTemplate.scala 92:22]
    node waymask = mux(resetState, UInt<1>("h01"), UInt<1>("h01")) @[SRAMTemplate.scala 93:20]
    wire wdata : UInt<72>[1] @[SRAMTemplate.scala 94:22]
    wdata[0] <= wdataword @[SRAMTemplate.scala 94:22]
    when wen : @[SRAMTemplate.scala 95:14]
      node _T_12 = bits(waymask, 0, 0) @[SRAMTemplate.scala 95:51]
      node _T_13 = or(setIdx, UInt<7>("h00"))
      node _T_14 = bits(_T_13, 6, 0)
      write mport _T_15 = array[_T_14], clock
      when _T_12 :
        _T_15[0] <= wdata[0]
        skip
      skip @[SRAMTemplate.scala 95:14]
    wire _T_16 : UInt @[Hold.scala 28:87]
    _T_16 is invalid @[Hold.scala 28:87]
    when realRen : @[Hold.scala 28:87]
      _T_16 <= io.r.req.bits.setIdx @[Hold.scala 28:87]
      node _T_17 = or(_T_16, UInt<7>("h00")) @[Hold.scala 28:87]
      node _T_18 = bits(_T_17, 6, 0) @[Hold.scala 28:87]
      read mport _T_19 = array[_T_18], clock @[Hold.scala 28:87]
      skip @[Hold.scala 28:87]
    reg _T_20 : UInt<1>, clock @[Hold.scala 28:106]
    _T_20 <= realRen @[Hold.scala 28:106]
    wire _T_21 : UInt<72>[1] @[Hold.scala 23:81]
    _T_21[0] <= UInt<72>("h00") @[Hold.scala 23:81]
    reg _T_22 : UInt<72>[1], clock with : (reset => (reset, _T_21)) @[Reg.scala 27:20]
    when _T_20 : @[Reg.scala 28:19]
      _T_22[0] <= _T_19[0] @[Reg.scala 28:23]
      skip @[Reg.scala 28:19]
    node _T_23 = mux(_T_20, _T_19, _T_22) @[Hold.scala 23:48]
    wire rdata_0 : {tag : UInt<29>, _type : UInt<2>, target : UInt<39>, lateJump : UInt<1>, valid : UInt<1>} @[SRAMTemplate.scala 98:78]
    wire _T_24 : UInt<72>
    _T_24 <= _T_23[0]
    node _T_25 = bits(_T_24, 0, 0) @[SRAMTemplate.scala 98:78]
    rdata_0.valid <= _T_25 @[SRAMTemplate.scala 98:78]
    node _T_26 = bits(_T_24, 1, 1) @[SRAMTemplate.scala 98:78]
    rdata_0.lateJump <= _T_26 @[SRAMTemplate.scala 98:78]
    node _T_27 = bits(_T_24, 40, 2) @[SRAMTemplate.scala 98:78]
    rdata_0.target <= _T_27 @[SRAMTemplate.scala 98:78]
    node _T_28 = bits(_T_24, 42, 41) @[SRAMTemplate.scala 98:78]
    rdata_0._type <= _T_28 @[SRAMTemplate.scala 98:78]
    node _T_29 = bits(_T_24, 71, 43) @[SRAMTemplate.scala 98:78]
    rdata_0.tag <= _T_29 @[SRAMTemplate.scala 98:78]
    wire _T_30 : {tag : UInt<29>, _type : UInt<2>, target : UInt<39>, lateJump : UInt<1>, valid : UInt<1>}[1] @[SRAMTemplate.scala 99:28]
    _T_30[0].valid <= rdata_0.valid @[SRAMTemplate.scala 99:28]
    _T_30[0].lateJump <= rdata_0.lateJump @[SRAMTemplate.scala 99:28]
    _T_30[0].target <= rdata_0.target @[SRAMTemplate.scala 99:28]
    _T_30[0]._type <= rdata_0._type @[SRAMTemplate.scala 99:28]
    _T_30[0].tag <= rdata_0.tag @[SRAMTemplate.scala 99:28]
    io.r.resp.data[0].valid <= _T_30[0].valid @[SRAMTemplate.scala 99:18]
    io.r.resp.data[0].lateJump <= _T_30[0].lateJump @[SRAMTemplate.scala 99:18]
    io.r.resp.data[0].target <= _T_30[0].target @[SRAMTemplate.scala 99:18]
    io.r.resp.data[0]._type <= _T_30[0]._type @[SRAMTemplate.scala 99:18]
    io.r.resp.data[0].tag <= _T_30[0].tag @[SRAMTemplate.scala 99:18]
    node _T_31 = eq(resetState, UInt<1>("h00")) @[SRAMTemplate.scala 101:21]
    node _T_32 = eq(wen, UInt<1>("h00")) @[SRAMTemplate.scala 101:53]
    node _T_33 = and(_T_31, _T_32) @[SRAMTemplate.scala 101:33]
    io.r.req.ready <= _T_33 @[SRAMTemplate.scala 101:18]
    io.w.req.ready <= UInt<1>("h01") @[SRAMTemplate.scala 102:18]

Is there a plan to support the new version of FIRRTL?

[sbeamer]

Yes!

Unfortunately, it might take us 3 weeks to get to FIRRTL 1.3.2 support, but that is next on our list.

[sashimi-yzh]

Amazing! I am looking forward to the new version! :)

[sashimi-yzh]

I found that using low firrtl can pass the compilation. Now my project can run with essent.

[sbeamer]

We support at least FIRRTL 1.3.1. Does that help?

[sashimi-yzh]

It works!

But when I try with another project using FIRRTL 1.4.0, essent (commit c062973) still reports error. I upload the fir file here. The error says:

Exception in thread "main" scala.MatchError: WSubAccess(WRef(bankHitWays,VectorType(UIntType(IntWidth(1)),16),WireKind,SourceFlow),WSubIndex(WRef(bankIdxInOrder,VectorType(UIntType(IntWidth(4)),16),WireKind,SourceFlow),0,UIntType(IntWidth(4)),SourceFlow),UIntType(IntWidth(1)),SourceFlow) (of class firrtl.WSubAccess)
        at firrtl.passes.LowerTypes$.lowerTypesExp(LowerTypes.scala:147)
        at firrtl.passes.LowerTypes$.$anonfun$lowerTypesExp$5(LowerTypes.scala:165)
        at scala.collection.TraversableLike.$anonfun$map$1(TraversableLike.scala:273)
        at scala.collection.immutable.List.foreach(List.scala:392)
        at scala.collection.TraversableLike.map(TraversableLike.scala:273)
        at scala.collection.TraversableLike.map$(TraversableLike.scala:266)
        at scala.collection.immutable.List.map(List.scala:298)
        at firrtl.ir.DoPrim.mapExpr(IR.scala:246) 
......

[sbeamer]

We now support 1.4.3. Hopeuflly we will be quicker to support 1.5.0 when it is released.