Some verilog designs for an icestick40
puck*: yet another 8-bit cpu on a small fpga
There have been plenty of inspirational projects (swapforth, nopcpu to name a few) but I wanted to start from scratch and document my findings, especially those related to Verilog, the hardware description language I have chosen to define my CPU with.
*) Puck is named after one of our Pigmy goats because it is small and fun :-)
All major components are implemented, both software and hardware, and available in the repository. Currently writing test programs and some documentation. Next steps will be about optimizing the current design and sharing lessons learned.
My development platform
- yosys/icestorm on Ubuntu
I won't document the installation process. just check the Icestorm site and follow the instructions and the components will work out of the box.
- a Lattice IceStick
The iCEstick is pretty powerful (should be able to run at clockspeeds well over 100 MHz), affordable and easy to use with its USB connector. it is not really large but big enough to implement an 8-bit processor, complete with ram, a serial interface (uart) and a small monitor mode to load/save data to memory and start a program
- the IceBreaker board
i have also ordered an IceBreaker board which has more logic cells as well as dedicated DSP options (and having hardware multipliers is nice for a CPU)
- an 8-bit cpu
This the main goal and for me the fun part: designing and implementing a decent instruction set. Not just an ALU but also branch instructions and a return stack so that we can write subroutines.
- a monitor program
A monitor program is some hardware that allows you to inspect memory, upload bytes and run a program. you could of course create your hardware with a fixed program in rom but in my thinking a monitor program is essential for testing your designs quickly. That's why this component was actually the first I implemented.
It comes in two parts: hardware to load and dump memory contents, and a python program to make life a bit easier.
The hardware part is implemented in the toplevel puck.v file. The python front-end is in a folder of iets own along with some documentatiin.
The hardware is mainly about reusing an existing uart design and making our first steps into Verilog.
- an assembler
Writing any kind of machine code by hand quickly becomes unwieldy and error prone. so an assembler, even a rather simplistic one, is a must have. Writing one in Python is straightforward so i'll certainly create one.
I mention this as a goal in itself because for me it is important to understand whatever I find out so that others (or myself at a later point) do not have to reinvent the wheel
- and finally, a calculator program
It will read input lines, parse numbers and operators amd perform simple calculations