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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,19 @@ | ||
| #!/usr/bin/perl | ||
| if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } | ||
| # DESCRIPTION: Verilator: Verilog Test driver/expect definition | ||
| # | ||
| # Copyright 2003 by Wilson Snyder. This program is free software; you can | ||
| # redistribute it and/or modify it under the terms of either the GNU | ||
| # Lesser General Public License Version 3 or the Perl Artistic License | ||
| # Version 2.0. | ||
|
|
||
| compile ( | ||
| verilator_flags2=>["-Wno-UNOPTFLAT"], | ||
| ); | ||
|
|
||
| execute ( | ||
| check_finished=>1, | ||
| ); | ||
|
|
||
| ok(1); | ||
| 1; |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,90 @@ | ||
| // DESCRIPTION: Verilator: Verilog Test module | ||
| // | ||
| // This file ONLY is placed into the Public Domain, for any use, | ||
| // without warranty, 2012 by Wilson Snyder. | ||
|
|
||
| module t (/*AUTOARG*/ | ||
| // Inputs | ||
| clk | ||
| ); | ||
| input clk; | ||
|
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| integer cyc=0; | ||
| reg [63:0] crc; | ||
| reg [63:0] sum; | ||
|
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| // Take CRC data and apply to testblock inputs | ||
| wire [31:0] in = crc[31:0]; | ||
|
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| /*AUTOWIRE*/ | ||
| // Beginning of automatic wires (for undeclared instantiated-module outputs) | ||
| wire [31:0] out; // From test of Test.v | ||
| // End of automatics | ||
|
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| Test test (/*AUTOINST*/ | ||
| // Outputs | ||
| .out (out[31:0]), | ||
| // Inputs | ||
| .clk (clk), | ||
| .in (in[31:0])); | ||
|
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| // Aggregate outputs into a single result vector | ||
| wire [63:0] result = {32'h0, out}; | ||
|
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| // Test loop | ||
| always @ (posedge clk) begin | ||
| `ifdef TEST_VERBOSE | ||
| $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); | ||
| `endif | ||
| cyc <= cyc + 1; | ||
| crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; | ||
| sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; | ||
| if (cyc==0) begin | ||
| // Setup | ||
| crc <= 64'h5aef0c8d_d70a4497; | ||
| sum <= 64'h0; | ||
| end | ||
| else if (cyc<10) begin | ||
| sum <= 64'h0; | ||
| end | ||
| else if (cyc<90) begin | ||
| end | ||
| else if (cyc==99) begin | ||
| $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); | ||
| if (crc !== 64'hc77bb9b3784ea091) $stop; | ||
| // What checksum will we end up with (above print should match) | ||
| `define EXPECTED_SUM 64'h458c2de282e30f8b | ||
| if (sum !== `EXPECTED_SUM) $stop; | ||
| $write("*-* All Finished *-*\n"); | ||
| $finish; | ||
| end | ||
| end | ||
|
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| endmodule | ||
|
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| module Test (/*AUTOARG*/ | ||
| // Outputs | ||
| out, | ||
| // Inputs | ||
| clk, in | ||
| ); | ||
|
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| input clk; | ||
| input [31:0] in; | ||
| output wire [31:0] out; | ||
|
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| reg [31:0] stage [3:0]; | ||
|
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| genvar g; | ||
|
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| generate | ||
| for (g=0; g<4; g++) begin | ||
| always_comb begin | ||
| if (g==0) stage[g] = in; | ||
| else stage[g] = {stage[g-1][30:0],1'b1}; | ||
| end | ||
| end | ||
| endgenerate | ||
|
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| assign out = stage[3]; | ||
| endmodule |