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wreal implicit assignments don't reevaluate #1150

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veripoolbot opened this issue Mar 30, 2017 · 4 comments
Closed

wreal implicit assignments don't reevaluate #1150

veripoolbot opened this issue Mar 30, 2017 · 4 comments

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@veripoolbot veripoolbot commented Mar 30, 2017


Author Name: j briquet
Original Redmine Issue: 1150 from https://www.veripool.org

Original Assignee: Wilson Snyder (@wsnyder)


Hello,

I am currently using Verilator's tool to convert some wreal models in SystemC, knowing some limitations or unsupported features.
As for now, I was able to verilate some basics models. But, I recently faced an issue when substracting two wreal signals, to evaluate if the result is within or not a certain range. Actually, if you refer to the below code, I observed that the intermediate signal "in_int" stays always to 0.0 when vin > gnd.
I created a very simple test case with a systemC testbench, that you can find in attachment. To run it, just need to go to test_sc and type the command : make .

Best regards,
J-P

module within_range(vin,gnd,out);

input vin;
input gnd;
output out;

parameter real V_MIN = 0.5;
parameter real V_MAX = 10;

`begin_keywords "1800+VAMS"
wreal vin;
wreal gnd;
wreal in_int = vin - gnd;
wire out = (V_MIN <= in_int && in_int <= V_MAX);

`end_keywords

endmodule

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@veripoolbot veripoolbot commented Mar 30, 2017


Original Redmine Comment
Author Name: j briquet
Original Date: 2017-03-30T08:18:46Z


Please find all the necessary files, tar file seems to be filtered. If you need more information, please do not hesitate.
Thanks,
J-P

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@veripoolbot veripoolbot commented Mar 30, 2017


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-03-30T22:36:13Z


As you noted AMS doesn't have much support, but this certainly should have worked. Turns out it was incorrectly ignoring the continuous assignment aspect. Thanks for the test.

Fixed in git towards 3.902.

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@veripoolbot veripoolbot commented Mar 30, 2017


Original Redmine Comment
Author Name: j briquet
Original Date: 2017-03-30T23:26:09Z


Thanks for your quick support, I will give it a try later and let you know. J-P

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@veripoolbot veripoolbot commented Apr 2, 2017


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-04-02T12:52:54Z


In 3.902.

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