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Add XSim support to driver.pl #1493

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veripoolbot opened this issue Aug 29, 2019 · 3 comments
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Add XSim support to driver.pl #1493

veripoolbot opened this issue Aug 29, 2019 · 3 comments

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@veripoolbot veripoolbot commented Aug 29, 2019


Author Name: Todd Strader (@toddstrader)
Original Redmine Issue: 1493 from https://www.veripool.org

Original Assignee: Todd Strader (@toddstrader)


Related to #�:
https://github.com/toddstrader/verilator-dev/tree/xsim

This is particularly useful to me because, while the free-ish version of ModelSim is my go-to simulator for personal machine hacking it requires that you build DPI objects with an ancient compiler and cross compile them as 32-bit objects. XSim also has a free-ish version but doesn't suffer from these DPI issues.

Given what's currently in the branch I was able to get:

TESTS DONE, FAILED: Passed 495  Failed 308  Failed-First 0  Skipped 1  Unsup 1  Time 208:19

I'm not actually sure what the time was because two tests got stuck. And I'm frankly surprised it did this well with so little work.

I've never run driver.pl against a simulator other than Verilator, so I'm not sure how this is supposed to work. Does this indicate that only three tests need to be skipped for VCS to run cleanly?

$ grep "vcs.*unsupported" t/t*.pl
t/t_interface_down_gen.pl:$Self->{vcs} and unsupported("Commercially unsupported, interface crossrefs");
t/t_math_precedence.pl:#!$Self->{vcs} or unsupported("VCS does ** wrong, fixed in 2014");
t/t_package_export.pl:$Self->{vcs} and unsupported("VCS unsupported");

Do all the other simulators run cleanly if you just run driver.pl --other_guy? Or rather, what kind of state would I need to get this in before pushing?

Are the command line arguments in input.vc defined in some standard? I searched the LRM for "librescan" but couldn't find it. Is there a separate spec for these things? Or is this just an EDA gentlemen's agreement? Either way, I had to make input.xsim.vc for this to work. Also, +define is --define in XSim for whatever reason.

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@veripoolbot veripoolbot commented Aug 29, 2019


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-08-29T14:30:42Z


These changes seem fine, you can squash and merge them as you feel appropriate.

When debugging a single test I sometimes add the skips so I remember that it fails on another simulator. I have not made an effort to get the whole regression passing/skipping on any simulator other than verilator. If you want to look into cleaning them up, that's great.

The "defacto" standard for flags is a subset of what Verilog-XL defined, and basically a gentlemen's agreement. If you google "Verilog-XL manual" you'll find something.

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@veripoolbot veripoolbot commented Aug 29, 2019


Original Redmine Comment
Author Name: Todd Strader (@toddstrader)
Original Date: 2019-08-29T21:03:55Z


Great, thanks for the info. This is squashed and pushed now.

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@veripoolbot veripoolbot commented Aug 29, 2019


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-08-29T23:14:24Z


In 4.018.

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