Verilator shows an internal error if a module that has inout ports is not inlined

[yTakatsukasa]

If a module that has inout port is not inlined, verilator shows the following internal error.

%Error: Internal Error: t/t_tri_inout.v:8:32: ../V3Gate.cpp:1103: Consumer doesn't match lhs of assign
    8 |    io   io1(.A(A), .OE( SEL), .Z(Z), .Y(Y1));
      |                                ^
                        ... See the manual at https://verilator.org/verilator_doc.html for more assistance.
%Warning: vlt/t_tri_inout: Exec of perl failed: %Error: Internal Error: t/t_tri_inout.v:8:32: ../V3Gate.cpp:1103: Consumer doesn't match lhs of assign

This error can be easily reproduced by adding /*verilator no_inline_module*/ metacomment to io module in t_tri_inout.v

verilator/test_regress/t/t_tri_inout.v

Lines 18 to 22 in fd45be3

	module io (input A, input OE, inout Z, output Y);
	assign Z = (OE) ? A : 1'bz;
	assign Y = Z;
	assign Z = 1'bz;
	endmodule

Passing -Od to skip dedupe optimization allows verilation, but the simulation result is not good.
I assume the optimization pass is essential.

The quickest fix would be forcing the module to be inlined regardless of its size, but not ideal of course.

I am trying to understand what dedupe optimization does and hopefully find better fix.
Any suggestion will be appreciated.

[yTakatsukasa]

I don't fully understand tri-state handling yet, but output of V3Tristate looks strange.
__en declared as input but used as LHS.

    1:2: ASSIGNW 0xefa4a0 <e1071#> {d10al} @dt=0xeddc30@(G/w1)
    1:2:1: OR 0xefa150 <e1068#> {d10al} @dt=0xef11b0@(G/w1)
    1:2:1:1: OR 0xef92e0 <e1044#> {d9bi} @dt=0xef11b0@(G/w1)
    1:2:1:1:1: VARREF 0xef84e0 <e995#> {d8bi} @dt=0xef11b0@(G/w1)  Z__out__en2 [RV] <- VAR 0xef7de0 <e935#> {d7ct} @dt=0xef11b0@(G/w1)  Z__out__en2 MODULETEMP
    1:2:1:1:2: VARREF 0xef91d0 <e996#> {d9bi} @dt=0xef11b0@(G/w1)  Z__out__en3 [RV] <- VAR 0xef8a10 <e972#> {d7ct} @dt=0xef11b0@(G/w1)  Z__out__en3 MODULETEMP
    1:2:1:2: VARREF 0xefa040 <e1045#> {d10al} @dt=0xef11b0@(G/w1)  Z__out__en4 [RV] <- VAR 0xef9880 <e1021#> {d7ct} @dt=0xef11b0@(G/w1)  Z__out__en4 MODULETEMP
    1:2:2: VARREF 0xefa560 <e1069#> {d7ct} @dt=0xeddc30@(G/w1)  Z__en [LV] => VAR 0xef7a10 <e920#> {d7ct} @dt=0xeddc30@(G/w1)  Z__en INPUT MODULETEMP

Comment tells __en and __out are output Inlining hides this mismatch ? Will read V3Tristate more.

verilator/src/V3Tristate.cpp

Lines 48 to 50 in fd45be3

	// suffixes __en and __out. The original port is turned from an inout
	// to an input and the __out port carries the output driver signal and
	// the __en port carried the output enable for that driver.

[wsnyder]

I suspect dedup is just catching the problem and not really related to the real issue with tristate. It looks like the variable does have the wrong direction as you suggest - does fixing that make it work?