Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Linter allows commas in instance parameters where they are not allowed in Verilog #4979

Closed
paul-demo opened this issue Mar 13, 2024 · 4 comments
Labels
area: lint Issue involves SystemVerilog lint checking area: parser Issue involves SystemVerilog parsing resolution: fixed Closed; fixed

Comments

@paul-demo
Copy link
Contributor

Verilator's linter is fine with the following trailing comma in parameter list. Most other tools, and I think the language Verilog in general, do not allow a comma after PARAM_A here:

  some_module #(
      .PARAM_A(1),
  ) some_module_inst (
      .clk(clk),
      .reset(reset)
  );

I can probably fix it if you point me to the right files to change.

@paul-demo paul-demo added the new New issue not seen by maintainers label Mar 13, 2024
@wsnyder wsnyder added area: lint Issue involves SystemVerilog lint checking status: ready Issue is ready for someone to fix; then goes to 'status: assigned' and removed new New issue not seen by maintainers labels Mar 14, 2024
@wsnyder
Copy link
Member

wsnyder commented Mar 14, 2024

If you could create a pull to add a test (e.g. t_param_comma_bad.v/.pl/out) that would be appreciated. Please also check for a similar problem with class parameters.

Empty pins are allowed in the parser and reported later in V3LinkCells, so probably there's a check needed there for parameters.

@paul-demo
Copy link
Contributor Author

paul-demo commented Mar 22, 2024

I didn't see a simple way to fix it. Currently, you look for things with name="" and give them some default param name. However, maybe you also need to check if the value even exists or if it's also empty, and throw a PINNOCONNECT error like you do some of the time.

I didn't get to actually fixing it but wrote down the test cases which succeed even though they should fail:
#5012

It happens when you have > 1 parameter, and you specify 1 parameter with a comma suggesting you were also filling out the second parameter (though it isn't included). Hopefully that makes sense; see the .v files in the PR.

@paul-demo
Copy link
Contributor Author

paul-demo commented Mar 22, 2024

Note: it may be PINNOTFOUND in V3LinkDot.cpp that needs to be changed. That's at least the error message displayed in the other cases. Specifically, it might be this function that needs to be updated:

void visit(AstPin* nodep) override {

Edit: actually now that I think about it some more, probably foundp is returning true for the empty/missing second parameter (the one created from the nothingness after the trailing comma) since there is a second parameter in the module/class definition. Maybe you're right and it shouldn't even be creating the second, empty/default-named parameter in V3LinkCells.

@wsnyder wsnyder added resolution: fixed Closed; fixed area: parser Issue involves SystemVerilog parsing and removed status: ready Issue is ready for someone to fix; then goes to 'status: assigned' labels Apr 30, 2024
@wsnyder
Copy link
Member

wsnyder commented Apr 30, 2024

Thanks for the test cases & looking into this. I realized we could alternatively change the grammar to fix this, so committed that.

@wsnyder wsnyder closed this as completed Apr 30, 2024
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
area: lint Issue involves SystemVerilog lint checking area: parser Issue involves SystemVerilog parsing resolution: fixed Closed; fixed
Projects
None yet
Development

No branches or pull requests

2 participants