Fix comparison of data types

[tastynoob]

related issue #4443

i found commit 5126689 cause unpredictable problems in rtl emulation

and this bug exists in subsequent versions

it may produce unpredictable conditional logic and value errors

[tastynoob]

i think verilator need add large projects to the test set
there must be many more bugs introduced like this

[wsnyder]

We need a small self-checking test case to know what to do to fix this.

Larger test cases are in https://github.com/verilator/verilator_ext_tests if you have a project that meets the criteria please open a separate issue on that and we'll discuss.

[wsnyder]

Of course a pull to fix it would also be appreciated (with the small test).

[tastynoob]

Of course a pull to fix it would also be appreciated (with the small test).

sure, i will try to fix it

[tastynoob]

a stupid way to fix it:
add code
if (node1p->dtypep() != node2p->dtypep()) return false;
after this

verilator/src/V3Ast.cpp

Line 1101 in 88831ca

if (node1p->type() != node2p->type()) return false;

i found it may produce wrong logic at complex scene
I really have no way to find a simple test to reproduce this bug

in my CPU, this bug will cause a module's output not assigned correctly
i extract this module separately, it can't reproduce
but at least after applying this fix, my CPU works perfectly

[tastynoob]

NOTE: this fix will cause #4308 test fail
i will find a better way to fix it

[tastynoob]

it should use:
if (!VN_IS(node1p->dtypep(), BasicDType) && (node1p->dtypep() != node2p->dtypep())) return false;
and it works perfectly at my designed CPU and #4308

if you has no objection, i will create one pr
@wsnyder

[wsnyder]

Sure, please make a PR, we'll need a small test with that, thanks!

[tastynoob]

can i ask about the progress?

[wsnyder]

Waiting on your pull request.

[tastynoob]

Waiting on your pull request.

here #5008