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[Odin]: - refactoring techmap_heavysuite for yosys+odin
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	- adding koios benchmark to techmap heavysuite for yosys+odin

Signed-off-by: Seyed Alireza Damghani <sdamghan@unb.ca>
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@sdamghan
sdamghan committed Aug 10, 2021
1 parent 23ee3af commit d302dcc
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Showing 152 changed files with 551,087 additions and 1,499 deletions.
2 changes: 1 addition & 1 deletion ODIN_II/SRC/Yosys.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -48,7 +48,7 @@
*/
Yosys::Yosys() {
/* to check if Yosys is installed */
FILE* fp = run_cmd(this->which_yosys, "r");
FILE* fp = run_cmd(this->which_yosys.c_str(), "r");
char* retval = NULL;
vtr::getline(retval, fp);
int exit_code = WEXITSTATUS(pclose(fp));
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2 changes: 1 addition & 1 deletion ODIN_II/SRC/include/Yosys.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -80,7 +80,7 @@ class Yosys {
std::string log;
std::string blif;
std::string executable;
const char* which_yosys = std::string("which yosys").c_str();
std::string which_yosys = std::string("which yosys");

private:
std::string tcl_primitives;
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24 changes: 6 additions & 18 deletions ODIN_II/SRC/memories.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1273,13 +1273,11 @@ bool is_blif_sp_ram(nnode_t* node) {
oassert(node->name);
/* return value */
bool is_ram = true;
char* hard_block_name = (configuration.coarsen) ? get_stripped_name(node->name) : node->name;
char* hard_block_identifier = get_hard_block_node_name(hard_block_name);
if (std::string(node->name).find(SINGLE_PORT_RAM_string) == std::string::npos)
return false;

/* check the num input/output ports */
is_ram = (!strcmp(hard_block_identifier, SINGLE_PORT_RAM_string))
&& (node->num_input_port_sizes == 4)
&& (node->num_output_port_sizes == 1);
is_ram = (node->num_input_port_sizes == 4) && (node->num_output_port_sizes == 1);

/* check if it is a ram */
if (is_ram) {
Expand Down Expand Up @@ -1307,10 +1305,6 @@ bool is_blif_sp_ram(nnode_t* node) {
}
}

// CLEAN UP
vtr::free(hard_block_name);
vtr::free(hard_block_identifier);

return (is_ram);
}

Expand All @@ -1326,13 +1320,11 @@ bool is_blif_dp_ram(nnode_t* node) {
oassert(node->name);
/* return value */
bool is_ram = true;
char* hard_block_name = (configuration.coarsen) ? get_stripped_name(node->name) : node->name;
char* hard_block_identifier = get_hard_block_node_name(hard_block_name);
if (std::string(node->name).find(DUAL_PORT_RAM_string) == std::string::npos)
return false;

/* check the num input/output ports */
is_ram = (!strcmp(hard_block_identifier, DUAL_PORT_RAM_string))
&& (node->num_input_port_sizes == 7)
&& (node->num_output_port_sizes == 2);
is_ram = (node->num_input_port_sizes == 7) && (node->num_output_port_sizes == 2);

/* check if it is a ram */
if (is_ram) {
Expand Down Expand Up @@ -1360,10 +1352,6 @@ bool is_blif_dp_ram(nnode_t* node) {
}
}

// CLEAN UP
vtr::free(hard_block_name);
vtr::free(hard_block_identifier);

return (is_ram);
}

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6 changes: 5 additions & 1 deletion ODIN_II/SRC/netlist_utils.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -911,7 +911,8 @@ signal_list_t* prune_signal(signal_list_t* signalsvar, long signal_width, long p
/* pruning the extra pins */
else {
/* detach from the node, its net and free pin */
delete_npin(pin);
pin->node->input_pins[pin->pin_node_idx] = NULL;
pin->node = NULL;
warning_message(NETLIST, unknown_location,
"Input pin (%s) exceeds the size of its connected port, will be left unconnected", pin->net->name);
}
Expand All @@ -924,6 +925,9 @@ signal_list_t* prune_signal(signal_list_t* signalsvar, long signal_width, long p
/* combining pruned signals */
new_signals = combine_lists(splitted_signals, num_of_signals);

// CLEAN UP
vtr::free(splitted_signals);

return (new_signals);
}

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1 change: 1 addition & 0 deletions ODIN_II/regression_test/benchmark/suite/yosys+odin/techmap_heavysuite/task_list.conf
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Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
regression_test/benchmark/task/yosys+odin/FIR
regression_test/benchmark/task/yosys+odin/koios
regression_test/benchmark/task/yosys+odin/full
regression_test/benchmark/task/yosys+odin/large
regression_test/benchmark/task/yosys+odin/vtr
76 changes: 32 additions & 44 deletions ODIN_II/regression_test/benchmark/task/yosys+odin/common/simulation_result.json
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Original file line number Diff line number Diff line change
Expand Up @@ -287,16 +287,14 @@
"exec_time(ms)": 110,
"simulation_time(ms)": 5.4,
"test_coverage(%)": 100,
"Latch Drivers": 1,
"Pi": 4,
"Pi": 3,
"Po": 2,
"logic element": 9,
"latch": 2,
"logic element": 4,
"generic logic size": 4,
"Longest Path": 9,
"Average Path": 7,
"Estimated LUTs": 9,
"Total Node": 12
"Longest Path": 4,
"Average Path": 4,
"Estimated LUTs": 4,
"Total Node": 4
},
"common/adlatch/no_arch": {
"test_name": "common/adlatch/no_arch",
Expand All @@ -305,15 +303,13 @@
"exec_time(ms)": 17.2,
"simulation_time(ms)": 5.2,
"test_coverage(%)": 100,
"Latch Drivers": 1,
"Pi": 4,
"Pi": 3,
"Po": 2,
"logic element": 9,
"latch": 2,
"Longest Path": 9,
"Average Path": 7,
"Estimated LUTs": 9,
"Total Node": 12
"logic element": 4,
"Longest Path": 4,
"Average Path": 4,
"Estimated LUTs": 4,
"Total Node": 4
},
"common/bitwise_not/k6_frac_N10_frac_chain_mem32K_40nm": {
"test_name": "common/bitwise_not/k6_frac_N10_frac_chain_mem32K_40nm",
Expand Down Expand Up @@ -596,16 +592,14 @@
"exec_time(ms)": 119.1,
"simulation_time(ms)": 5.1,
"test_coverage(%)": 100,
"Latch Drivers": 1,
"Pi": 3,
"Pi": 2,
"Po": 2,
"logic element": 2,
"latch": 2,
"generic logic size": 4,
"Longest Path": 5,
"Average Path": 4,
"Longest Path": 3,
"Average Path": 3,
"Estimated LUTs": 2,
"Total Node": 5
"Total Node": 2
},
"common/dlatch/no_arch": {
"test_name": "common/dlatch/no_arch",
Expand All @@ -614,15 +608,13 @@
"exec_time(ms)": 16.9,
"simulation_time(ms)": 5.1,
"test_coverage(%)": 100,
"Latch Drivers": 1,
"Pi": 3,
"Pi": 2,
"Po": 2,
"logic element": 2,
"latch": 2,
"Longest Path": 5,
"Average Path": 4,
"Longest Path": 3,
"Average Path": 3,
"Estimated LUTs": 2,
"Total Node": 5
"Total Node": 2
},
"common/ge/k6_frac_N10_frac_chain_mem32K_40nm": {
"test_name": "common/ge/k6_frac_N10_frac_chain_mem32K_40nm",
Expand Down Expand Up @@ -1437,16 +1429,14 @@
"exec_time(ms)": 125.5,
"simulation_time(ms)": 9.8,
"test_coverage(%)": 100,
"Latch Drivers": 3,
"Pi": 6,
"Pi": 3,
"Po": 3,
"logic element": 15,
"latch": 3,
"logic element": 6,
"generic logic size": 4,
"Longest Path": 8,
"Average Path": 6,
"Estimated LUTs": 15,
"Total Node": 21
"Longest Path": 4,
"Average Path": 4,
"Estimated LUTs": 6,
"Total Node": 6
},
"common/sr/no_arch": {
"test_name": "common/sr/no_arch",
Expand All @@ -1455,15 +1445,13 @@
"exec_time(ms)": 27.5,
"simulation_time(ms)": 12,
"test_coverage(%)": 100,
"Latch Drivers": 3,
"Pi": 6,
"Pi": 3,
"Po": 3,
"logic element": 15,
"latch": 3,
"Longest Path": 8,
"Average Path": 6,
"Estimated LUTs": 15,
"Total Node": 21
"logic element": 6,
"Longest Path": 4,
"Average Path": 4,
"Estimated LUTs": 6,
"Total Node": 6
},
"common/sub/k6_frac_N10_frac_chain_mem32K_40nm": {
"test_name": "common/sub/k6_frac_N10_frac_chain_mem32K_40nm",
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74 changes: 30 additions & 44 deletions ODIN_II/regression_test/benchmark/task/yosys+odin/common/synthesis_result.json
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Original file line number Diff line number Diff line change
Expand Up @@ -304,16 +304,14 @@
"optimization_time(ms)": 0,
"techmap_time(ms)": 0.1,
"synthesis_time(ms)": 50.8,
"Latch Drivers": 1,
"Pi": 4,
"Pi": 3,
"Po": 2,
"logic element": 7,
"latch": 2,
"logic element": 2,
"generic logic size": 4,
"Longest Path": 8,
"Average Path": 6,
"Estimated LUTs": 7,
"Total Node": 10
"Longest Path": 3,
"Average Path": 3,
"Estimated LUTs": 2,
"Total Node": 2
},
"common/adlatch/no_arch": {
"test_name": "common/adlatch/no_arch",
Expand All @@ -324,15 +322,13 @@
"optimization_time(ms)": 0,
"techmap_time(ms)": 0.1,
"synthesis_time(ms)": 46.3,
"Latch Drivers": 1,
"Pi": 4,
"Pi": 3,
"Po": 2,
"logic element": 7,
"latch": 2,
"Longest Path": 8,
"Average Path": 6,
"Estimated LUTs": 7,
"Total Node": 10
"logic element": 2,
"Longest Path": 3,
"Average Path": 3,
"Estimated LUTs": 2,
"Total Node": 2
},
"common/bitwise_not/k6_frac_N10_frac_chain_mem32K_40nm": {
"test_name": "common/bitwise_not/k6_frac_N10_frac_chain_mem32K_40nm",
Expand Down Expand Up @@ -667,14 +663,11 @@
"optimization_time(ms)": 0,
"techmap_time(ms)": 0,
"synthesis_time(ms)": 32.2,
"Latch Drivers": 1,
"Pi": 3,
"Pi": 2,
"Po": 2,
"latch": 2,
"generic logic size": 4,
"Longest Path": 4,
"Average Path": 4,
"Total Node": 3
"Longest Path": 2,
"Average Path": 2
},
"common/dlatch/no_arch": {
"test_name": "common/dlatch/no_arch",
Expand All @@ -685,13 +678,10 @@
"optimization_time(ms)": 0,
"techmap_time(ms)": 0,
"synthesis_time(ms)": 44.7,
"Latch Drivers": 1,
"Pi": 3,
"Pi": 2,
"Po": 2,
"latch": 2,
"Longest Path": 4,
"Average Path": 4,
"Total Node": 3
"Longest Path": 2,
"Average Path": 2
},
"common/ge/k6_frac_N10_frac_chain_mem32K_40nm": {
"test_name": "common/ge/k6_frac_N10_frac_chain_mem32K_40nm",
Expand Down Expand Up @@ -1585,16 +1575,14 @@
"optimization_time(ms)": 0,
"techmap_time(ms)": 0.1,
"synthesis_time(ms)": 46.7,
"Latch Drivers": 3,
"Pi": 6,
"Pi": 3,
"Po": 3,
"logic element": 12,
"latch": 3,
"logic element": 3,
"generic logic size": 4,
"Longest Path": 7,
"Average Path": 6,
"Estimated LUTs": 12,
"Total Node": 18
"Longest Path": 3,
"Average Path": 3,
"Estimated LUTs": 3,
"Total Node": 3
},
"common/sr/no_arch": {
"test_name": "common/sr/no_arch",
Expand All @@ -1605,15 +1593,13 @@
"optimization_time(ms)": 0,
"techmap_time(ms)": 0.1,
"synthesis_time(ms)": 45.4,
"Latch Drivers": 3,
"Pi": 6,
"Pi": 3,
"Po": 3,
"logic element": 12,
"latch": 3,
"Longest Path": 7,
"Average Path": 6,
"Estimated LUTs": 12,
"Total Node": 18
"logic element": 3,
"Longest Path": 3,
"Average Path": 3,
"Estimated LUTs": 3,
"Total Node": 3
},
"common/sub/k6_frac_N10_frac_chain_mem32K_40nm": {
"test_name": "common/sub/k6_frac_N10_frac_chain_mem32K_40nm",
Expand Down
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