Issues with AUTOINOUTMODPORT and Handling Master and Slave interface names

[engrvns]

I am trying to convert a module with interface modports into SV ports by using a wrapper and AUTOINOUTMODPORT and AUTOASSIGNMODPORT.

Assume that the instance module has two interface mod-ports -
(1) AXI-Master axi_if.master
(2) AXI-Slave axi_if.slave
The signals names are exactly the same name in the axi_if mod ports.

Here are some of the issues I discovered in this scenario

Issue 1) Port creation gets skipped for the second mod-port.
When I use AUTOINOUTMODPORT to create ports as below
module wrapper (
/* AUTOINOUTMODPORT "axi_if" "master" / <- The ports get created.
/ AUTOINOUTMODPORT "axi_if" "slave" */ <- port creation gets skipped.

I am guessing that this happening because the signal names are same..
How does one resolve this issue...

Issue 2) AUTOASSIGNMODPORT expects 3 parameters but examples show 2 parameters

I am trying create assignments between the created SV ports and SV interface as -
/* AUTOASSIGNMODPORT "axi_if" "master" */
My expectation is that a bunch of assigns get created. But I get an error as "Expected 3 parameters"
The few examples shown has just 2 parameters.
What is the usage issue here..?

Issue 3) Appending a character to the created ports.
I further want to append the created SV-ports with a character such as "M" for master and "S" for slave.
How do we make this happen?

Thanks,
Engr

[engrvns]

Figured out the answer to Issue 3:
The third parameters is the instance name of the interface.
The correct usage should be -
/* AUTOASSIGNMODPORT "axi_if" "master" "interface_inst" */
This results in assign creation...

The examples need to be elaborated to show this 3rd parameter

[engrvns]

This extends the question in Issue 3 to AUTOASSIGNMODPORT as well.
How can users prefix or suffix the created wire names?

[wsnyder]

As to point 1, you are correct the second set is not created because the names are the same - this is a general verilog-mode rule that it won't declare something already declared.

As to point 2 there wasn't any example in the docs showing AUTOASSIGNMODPORT despite what the docs said. This is now fixed.

Looking at point 3, I understand your point, stay tuned.

[wsnyder]

Added support.

module ExampMain
  ( input clk,

    // Manually declared, so make sure not redeclared
    // Note this is AFTER addition of the prefix
    input       a_req_dat,

    /*AUTOINOUTMODPORT("ExampIf", "mp", "", "a_")*/
    // Beginning of automatic in/out/inouts (from modport)
    output      a_out,
    input       a_req_val,
    // End of automatics
    /*AUTOINOUTMODPORT("ExampIf", "mp", "", "b_")*/
    // Beginning of automatic in/out/inouts (from modport)
    output      b_out,
    input       b_req_val,
    input [7:0] b_req_dat
    // End of automatics
    );

   ExampleIf ia;
   ExampleIf ib;

   /*AUTOASSIGNMODPORT("ExampIf", "mp", "ia", "", "a_")*/
   // Beginning of automatic assignments from modport
   assign a_out = ia.out;
   assign ia.req_dat = a_req_dat;
   assign ia.req_val = a_req_val;
   // End of automatics
   /*AUTOASSIGNMODPORT("ExampIf", "mp", "ib", "", "b_")*/
   // Beginning of automatic assignments from modport
   assign b_out = ib.out;
   assign ib.req_dat = b_req_dat;
   assign ib.req_val = b_req_val;
   // End of automatics

endmodule