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#1163: fix for instance port indention inside generate for loop #1699

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#1163: fix for instance port indention inside generate for loop #1699

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@ruelparent ruelparent commented Oct 25, 2020 •
edited by wsnyder

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wsnyder added a commit that referenced this pull request Sep 16, 2021
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Fix instance port indention inside generate for loop (#1163) (#1699).
9def905 
* verilog-mode.el (verilog-in-generate-region-p):
Fix instance port indention inside generate for loop (#1163) (#1699).
Reported by ruelparent.
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wsnyder commented Sep 16, 2021

Hmm, seems like patch this wasn't based off master. Anyways I merged it manually, thanks for the contribution.

@wsnyder wsnyder closed this Sep 16, 2021
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ruelparent commented Sep 16, 2021 via email

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