Fix indentation of instances and declarations after 'begin' #1782
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* verilog-mode.el (verilog-beg-of-statement-1): Fix indentation of instances and declarations right after 'begin' Signed-off-by: Gonzalo Larumbe <gonzalomlarumbe@gmail.com>
wsnyder
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Jul 11, 2022
gmlarumbe
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Jul 11, 2022
Signed-off-by: Gonzalo Larumbe <gonzalomlarumbe@gmail.com>
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Hi,
While working on PR #1780 I noticed that a declaration that should get aligned for
indent_replicate.vactually did not. After a bit of debugging I found the issue was caused by the declaration being right after thebeginkeyword ifverilog-indent-listswas set to t (its default value).I applied part of the changes of 2adbba2 also for
verilog-indent-listsset to t and it happened to also fix theindent_genmod.vtest mentioned in #1163. Even though that issue shows as closed it seems this test was still broken, but it would be nice if it could be confirmed.Thanks!