Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

LSU transaction ID width #30

Closed
stevobailey opened this issue Jan 25, 2022 · 0 comments · Fixed by #33
Closed

LSU transaction ID width #30

stevobailey opened this issue Jan 25, 2022 · 0 comments · Fixed by #33

Comments

@stevobailey
Copy link
Contributor

vicuna/rtl/vproc_core.sv

Line 765 in 66ed264

logic lsu_trans_complete_id;

I think this signal should be XIF_ID_W bits wide, not 1 bit wide.
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Assignees
No one assigned
Labels
None yet
Projects
None yet
Milestone
No milestone
Development

Successfully merging a pull request may close this issue.

[stevo]: make lsu_trans_complete_id XIF_ID_W bits wide stevobailey/vicuna
1 participant
@stevobailey