- interim release w11a_V0.561 (untagged)

- Added simple simulation model of Cypress FX2 and test benches for functional verifcation of FX2 controller - Bugfixes in FX2 firmware and controller, works now also on Nexys3 & Atlys - Added test systems for rlink over USB verification for Nexys3 & Atlys
wfjm · Jan 6, 2013 · 29d2dc5 · 29d2dc5
1 parent cbd8ce3
commit 29d2dc5
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diff --git a/Makefile b/Makefile
@@ -1,4 +1,4 @@
-# $Id: Makefile 466 2012-12-30 13:26:55Z mueller $
+# $Id: Makefile 472 2013-01-06 14:39:10Z mueller $
 #
 # 'Meta Makefile' for whole retro project
 #   allows to make all synthesis targets
@@ -19,6 +19,9 @@ SYN_all += rtl/sys_gen/tst_rlink/nexys2
 SYN_all += rtl/sys_gen/tst_rlink/nexys3
 SYN_all += rtl/sys_gen/tst_rlink/s3board
 SYN_all += rtl/sys_gen/tst_rlink_cuff/nexys2/ic
+SYN_all += rtl/sys_gen/tst_rlink_cuff/nexys2/ic3
+SYN_all += rtl/sys_gen/tst_rlink_cuff/nexys3/ic
+SYN_all += rtl/sys_gen/tst_rlink_cuff/atlys/ic
 SYN_all += rtl/sys_gen/tst_serloop/nexys2
 SYN_all += rtl/sys_gen/tst_serloop/nexys3
 SYN_all += rtl/sys_gen/tst_serloop/s3board
@@ -34,6 +37,7 @@ SIM_all += rtl/bplib/nxcramlib/tb
 SIM_all += rtl/sys_gen/tst_rlink/nexys2/tb
 SIM_all += rtl/sys_gen/tst_rlink/nexys3/tb
 SIM_all += rtl/sys_gen/tst_rlink/s3board/tb
+SIM_all += rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb
 SIM_all += rtl/sys_gen/tst_serloop/nexys2/tb
 SIM_all += rtl/sys_gen/tst_serloop/nexys3/tb
 SIM_all += rtl/sys_gen/tst_serloop/s3board/tb

diff --git a/doc/README.txt b/doc/README.txt
@@ -1,4 +1,4 @@
-# $Id: README.txt 467 2013-01-02 19:49:05Z mueller $
+# $Id: README.txt 472 2013-01-06 14:39:10Z mueller $
 
 Release notes for w11a
 
@@ -40,7 +40,7 @@ Release notes for w11a
    rtl/sys_gen/tst_rlink          - top level designs for an rlink tester
      nexys2,nexys3,s3board          - systems for Nexsy2,Nexsy3,S3BOARD
    rtl/sys_gen/tst_rlink_cuff     - top level designs for rlink over FX2 tester
-     nexys2                         - systems for Nexsy2
+     nexys2,nexys3,atlys            - systems for Atlys,Nexsy2,Nexsy3
    rtl/sys_gen/tst_serloop        - top level designs for serport loop tester
      nexys2,nexys3,s3board          - systems for Nexsy2,Nexsy3,S3BOARD
    rtl/sys_gen/tst_snhumanio      - top level designs for human I/O tester
@@ -75,6 +75,26 @@ Release notes for w11a
 
 3. Change Log ----------------------------------------------------------------
 
+- trunk (2013-01-06: svn rev 18(oc) 472(wfjm); untagged w11a_V0.561) +++++++++
+
+  - Summary
+    - Added simple simulation model of Cypress FX2 and test benches for
+      functional verifcation of FX2 controller
+    - Bugfixes in FX2 firmware and controller, works now also on Nexys3 & Atlys
+    - Added test systems for rlink over USB verification for Nexys3 & Atlys
+
+  - New features
+    - new test benches
+      - rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb/tb_tst_rlink_cuff_ic_n2
+    - new systems
+      - rtl/sys_gen/tst_rlink_cuff/nexys2/ic/sys_tst_rlink_cuff_ic_n3
+      - rtl/sys_gen/tst_rlink_cuff/nexys2/ic/sys_tst_rlink_cuff_ic_atlys
+
+  - Bug fixes
+    - tools/fx2/src: FX2 firmware now properly re-initializes hardware registers
+        and will work on Nexys3 and Atlys boards with default Digilent EPROM
+    - rtl/bplib/fx2lib: read pipeline logic in FX2 controller corrected
+
 - trunk (2013-01-02: svn rev 17(oc) 467(wfjm); untagged w11a_V0.56) ++++++++++
 
   - Summary
@@ -89,7 +109,7 @@ Release notes for w11a
             in the file README_USB-VID-PID.txt. You'll be responsible for any
             misuse of the defaults provided with the project sources !!
 
-  - New refernce system
+  - New reference system
     The development and test system was upgraded from Kubuntu 10.04 to 12.04.
     The version of several key tools and libraries changed:
        linux kernel    3.2.0    (was  2.6.32)

diff --git a/doc/w11a_os_guide.txt b/doc/w11a_os_guide.txt
@@ -1,4 +1,4 @@
-# $Id: w11a_os_guide.txt 442 2011-12-23 10:03:28Z mueller $
+# $Id: w11a_os_guide.txt 469 2013-01-05 12:29:44Z mueller $
 
 Guide to run operating system images on w11a systems
 
@@ -52,7 +52,7 @@ Guide to run operating system images on w11a systems
 3. Unix V5 system ---------------------------------------------------------
 
    - A disk set is available from
-       http://www-linux.gsi.de/~mueller/retro/oc_w11/data/unix_v5_rkset.tgz
+       http://www.retro11.de/data/oc_w11/unix_v5_rkset.tgz
      Download, unpack and copy the disk images (*.dsk) to
        $RETROBASE/rtl/sys_gen/w11a/tb
 
@@ -97,7 +97,7 @@ Guide to run operating system images on w11a systems
 
 4. 2.11BSD system ---------------------------------------------------------
    - A disk set is available from
-       http://www-linux.gsi.de/~mueller/retro/oc_w11/data/211bsd_rkset.tgz
+       http://www.retro11.de/data/oc_w11/211bsd_rkset.tgz
      Download, unpack and copy the disk images (*.dsk) to
        $RETROBASE/rtl/sys_gen/w11a/tb
 

diff --git a/rtl/bplib/atlys/atlys_pins_fx2.ucf b/rtl/bplib/atlys/atlys_pins_fx2.ucf
@@ -0,0 +1,36 @@
+## $Id: atlys_pins_fx2.ucf 471 2013-01-05 19:46:38Z mueller $
+##
+## Revision History: 
+## Date         Rev Version  Comment
+## 2013-01-05   471   1.0    Initial version 
+##
+## Cypress EZ-USB FX2 Interface -- in Bank 0 ---------------------------------
+##
+##
+NET "I_FX2_IFCLK" LOC = "c10"    | IOSTANDARD=LVCMOS33;
+## 
+NET "IO_FX2_DATA<0>" LOC = "a2"  | IOSTANDARD=LVCMOS33;
+NET "IO_FX2_DATA<1>" LOC = "d6"  | IOSTANDARD=LVCMOS33;
+NET "IO_FX2_DATA<2>" LOC = "c6"  | IOSTANDARD=LVCMOS33;
+NET "IO_FX2_DATA<3>" LOC = "b3"  | IOSTANDARD=LVCMOS33;
+NET "IO_FX2_DATA<4>" LOC = "a3"  | IOSTANDARD=LVCMOS33;
+NET "IO_FX2_DATA<5>" LOC = "b4"  | IOSTANDARD=LVCMOS33;
+NET "IO_FX2_DATA<6>" LOC = "a4"  | IOSTANDARD=LVCMOS33;
+NET "IO_FX2_DATA<7>" LOC = "c5"  | IOSTANDARD=LVCMOS33;
+NET "IO_FX2_DATA<*>" DRIVE=12 | SLEW=FAST | KEEPER;
+##
+NET "O_FX2_SLWR_N" LOC = "e13"   | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
+NET "O_FX2_SLRD_N" LOC = "f13"   | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
+NET "O_FX2_SLOE_N" LOC = "a15"   | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
+##
+NET "O_FX2_PKTEND_N" LOC = "c4"  | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
+##
+NET "O_FX2_FIFO<0>" LOC = "a14"  | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
+NET "O_FX2_FIFO<1>" LOC = "b14"  | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
+##
+## assume that PA.7 is used as FLAGD (and not as SLCS#)
+NET "I_FX2_FLAG<0>" LOC = "b9"   | IOSTANDARD=LVCMOS33;   ## flag a (program)
+NET "I_FX2_FLAG<1>" LOC = "a9"   | IOSTANDARD=LVCMOS33;   ## flag b (full)
+NET "I_FX2_FLAG<2>" LOC = "c15"  | IOSTANDARD=LVCMOS33;   ## flag c (empty)
+NET "I_FX2_FLAG<3>" LOC = "b2"   | IOSTANDARD=LVCMOS33;   ## flag d (slcs)
+##
diff --git a/rtl/bplib/atlys/atlys_time_fx2_ic.ucf b/rtl/bplib/atlys/atlys_time_fx2_ic.ucf
@@ -0,0 +1,17 @@
+## $Id: atlys_time_fx2_ic.ucf 471 2013-01-05 19:46:38Z mueller $
+##
+## Revision History: 
+## Date         Rev Version  Comment
+## 2013-01-05   471   1.0    Initial version (copied from nexys3)
+##
+## timing rules for a 30 MHz internal clock design:
+##   Period:   30 MHz
+##   clk->out: longest setup time in FX2 is t_SRD (clk->SLRD) of 18.7 ns
+##               clk->out < 33.3-18.7 = 14.6 ns
+##               --> use 10 ns
+##
+
+NET "I_FX2_IFCLK" TNM_NET = "I_FX2_IFCLK";
+TIMESPEC "TS_I_FX2_IFCLK" = PERIOD "I_FX2_IFCLK" 33.34 ns HIGH 50 %;
+OFFSET =  IN  2 ns BEFORE "I_FX2_IFCLK";
+OFFSET = OUT 10 ns  AFTER "I_FX2_IFCLK";
diff --git a/rtl/bplib/bpgen/bpgenlib.vhd b/rtl/bplib/bpgen/bpgenlib.vhd
@@ -1,6 +1,6 @@
--- $Id: bpgenlib.vhd 426 2011-11-18 18:14:08Z mueller $
+-- $Id: bpgenlib.vhd 472 2013-01-06 14:39:10Z mueller $
 --
--- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
+-- Copyright 2011-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
 -- This program is free software; you may redistribute and/or modify it under
 -- the terms of the GNU General Public License as published by the Free
@@ -16,9 +16,10 @@
 -- Description:    Generic Board/Part components
 -- 
 -- Dependencies:   -
--- Tool versions:  12.1; ghdl 0.26-0.29
+-- Tool versions:  12.1, 13.3; ghdl 0.26-0.29
 -- Revision History: 
 -- Date         Rev Version  Comment
+-- 2013-01-06   472   1.0.7  add sn_humanio_demu_rbus
 -- 2011-11-16   426   1.0.6  now numeric_std clean
 -- 2011-10-10   413   1.0.5  add sn_humanio_demu
 -- 2011-08-07   404   1.0.4  add RELAY generic for bp_rs232_2l4l_iob
@@ -197,4 +198,25 @@ component sn_humanio_rbus is            -- human i/o handling /w rbus intercept
   );
 end component;
 
+component sn_humanio_demu_rbus is       -- human i/o swi,btn,led only /w rbus
+  generic (
+    DEBOUNCE : boolean := true;         -- instantiate debouncer for SWI,BTN
+    RB_ADDR : slv8 := slv(to_unsigned(2#10000000#,8)));
+  port (
+    CLK : in slbit;                     -- clock
+    RESET : in slbit := '0';            -- reset
+    CE_MSEC : in slbit;                 -- 1 ms clock enable
+    RB_MREQ : in rb_mreq_type;          -- rbus: request
+    RB_SRES : out rb_sres_type;         -- rbus: response
+    SWI : out slv8;                     -- switch settings, debounced
+    BTN : out slv4;                     -- button settings, debounced
+    LED : in slv8;                      -- led data
+    DSP_DAT : in slv16;                 -- display data
+    DSP_DP : in slv4;                   -- display decimal points
+    I_SWI : in slv8;                    -- pad-i: switches
+    I_BTN : in slv6;                    -- pad-i: buttons
+    O_LED : out slv8                    -- pad-o: leds
+  );
+end component;
+
 end package bpgenlib;
diff --git a/rtl/bplib/bpgen/sn_humanio_demu_rbus.vbom b/rtl/bplib/bpgen/sn_humanio_demu_rbus.vbom
@@ -0,0 +1,8 @@
+# libs
+../../vlib/slvtypes.vhd
+../../vlib/rbus/rblib.vhd
+bpgenlib.vbom
+# components
+sn_humanio_demu.vbom
+# design
+sn_humanio_demu_rbus.vhd