flowmap: implement depth relaxation.

passes/tests/flowmap/pack1.v

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+// Exact reproduction of Figure 3(a) from 10.1109/92.285741.
+module top(...);
+	input a,b,c,d,e,f,g,h;
+	wire x = !(c|d);
+	wire y = !(e&f);
+	wire u = !(a&b);
+	wire v = !(x|y);
+	wire w = !(g&h);
+	output s = !(u|v);
+	output t = !(v|w);
+endmodule

passes/tests/flowmap/pack1p.v

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+// Like pack1.v, but results in a simpler network.
+module top(...);
+	input a,b,c,d,e,f,g,h;
+	wire x = c|d;
+	wire y = e&f;
+	wire u = a&b;
+	wire v = x|y;
+	wire w = g&h;
+	output s = u|v;
+	output t = v|w;
+endmodule

passes/tests/flowmap/pack2.v

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+// Exact reproduction of Figure 4(a) from 10.1109/92.285741.
+module top(...);
+	(* $flowmap_level=1 *) input a;
+	(* $flowmap_level=1 *) input b;
+	(* $flowmap_level=2 *) input c;
+	(* $flowmap_level=1 *) input d;
+	(* $flowmap_level=3 *) input e;
+	(* $flowmap_level=1 *) input f;
+	wire u = !(a&b);
+	wire w = !(c|d);
+	wire v = !(u|w);
+	wire n0 = !(w&e);
+	wire n1 = !(n0|f);
+	output n2 = !(v&n1);
+endmodule

passes/tests/flowmap/pack2p.v

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+// Like pack2.v, but results in a simpler network.
+module top(...);
+	(* $flowmap_level=1 *) input a;
+	(* $flowmap_level=1 *) input b;
+	(* $flowmap_level=2 *) input c;
+	(* $flowmap_level=1 *) input d;
+	(* $flowmap_level=3 *) input e;
+	(* $flowmap_level=1 *) input f;
+	wire u = a&b;
+	wire w = c|d;
+	wire v = u|w;
+	wire n0 = w&e;
+	wire n1 = n0|f;
+	output n2 = v&n1;
+endmodule

passes/tests/flowmap/pack3.v

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+// Exact reproduction of Figure 5(a) (bottom) from 10.1109/92.285741.
+module top(...);
+	input a,b,c,d,e,f,g,h,i,j;
+	wire x = !(a&b);
+	wire y = !(c|d);
+	wire z = !(e|f);
+	wire n0 = !(g&h);
+	wire n1 = !(i|j);
+	wire w = !(x&y);
+	wire n2 = !(z&n0);
+	wire n3 = !(n0|n1);
+	wire n4 = !(n2|n3);
+	wire v = !(w|n5);
+	output u = !(w&v);
+endmodule

passes/tests/flowmap/pack3p.v

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+// Like pack2.v, but results in a simpler network.
+module top(...);
+	input a,b,c,d,e,f,g,h,i,j;
+	wire x = a&b;
+	wire y = c|d;
+	wire z = e|f;
+	wire n0 = g&h;
+	wire n1 = i|j;
+	wire w = x&y;
+	wire n2 = z&n0;
+	wire n3 = n0|n1;
+	wire n4 = n2|n3;
+	wire v = w|n5;
+	output u = w&v;
+endmodule