riscv32: use device tree defines in linker

Delete memory-related configs from defconfig and use device tree based macros in general riscv32 linker script instead of Kconfig ones. Signed-off-by: Filip Kokosinski <fkokosinski@internships.antmicro.com> Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
zephyrproject-rtos · May 10, 2019 · e0a8250 · e0a8250
1 parent 2b61c37
commit e0a8250
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Showing 3 changed files with 2 additions and 34 deletions.
diff --git a/include/arch/riscv32/common/linker.ld b/include/arch/riscv32/common/linker.ld
@@ -36,9 +36,9 @@
 MEMORY
 {
 #ifdef CONFIG_XIP
-    ROM (rx)  : ORIGIN = CONFIG_RISCV_ROM_BASE_ADDR, LENGTH = CONFIG_RISCV_ROM_SIZE
+    ROM (rx)  : ORIGIN = DT_FLASH_BASE_ADDRESS, LENGTH = KB(DT_FLASH_SIZE)
 #endif
-    RAM (rwx) : ORIGIN = CONFIG_RISCV_RAM_BASE_ADDR, LENGTH = RISCV_RAM_SIZE
+    RAM (rwx) : ORIGIN = DT_SRAM_BASE_ADDRESS, LENGTH = KB(DT_SRAM_SIZE)
     /* Used by and documented in include/linker/intlist.ld */
     IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K
 }

diff --git a/soc/riscv32/riscv-privilege/miv/Kconfig.defconfig.series b/soc/riscv32/riscv-privilege/miv/Kconfig.defconfig.series
@@ -30,20 +30,4 @@ config XIP
 	bool
 	default y
 
-config RISCV_ROM_BASE_ADDR
-	hex
-	default 0x80000000
-
-config RISCV_ROM_SIZE
-	hex
-	default 0x40000
-
-config RISCV_RAM_BASE_ADDR
-	hex
-	default	0x80040000
-
-config RISCV_RAM_SIZE
-	hex
-	default 0x40000
-
 endif # SOC_SERIES_RISCV32_MIV
diff --git a/soc/riscv32/riscv-privilege/sifive-freedom/Kconfig.defconfig.series b/soc/riscv32/riscv-privilege/sifive-freedom/Kconfig.defconfig.series
@@ -30,20 +30,4 @@ config XIP
 	bool
 	default y
 
-config RISCV_ROM_BASE_ADDR
-	hex
-	default 0x20400000
-
-config RISCV_ROM_SIZE
-	hex
-	default 0xC00000
-
-config RISCV_RAM_BASE_ADDR
-	hex
-	default	0x80000000
-
-config RISCV_RAM_SIZE
-	hex
-	default 0x4000
-
 endif # SOC_SERIES_RISCV32_SIFIVE_FREEDOM