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Cortex-R Port Improvement for 2.2 #19698
Cortex-R Port Improvement for 2.2 #19698
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Instead of making multiple PRs for various Cortex-R fix/refactoring/improvement tasks, I will be consolidating them all into this PR. Please do not merge this in the meantime. |
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Note for TEINIT and SCTLR.TE The rationale for this assumption is as follows:
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Some checks failed. Please fix and resubmit. checkpatch issues
Tip: The bot edits this comment instead of posting a new one, so you can check the comment's history to see earlier messages. |
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@ioannisg Here is the Cortex-R interrupt system changes.
@bbolen I have made some major changes to the Cortex-R port. It would be very helpful if you could review this. |
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Force-pushing to rebase onto the latest master and provide a minor inline asm styling fix (using |
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The current Cortex-R interrupt system relies on the multi-level interrupt mechanism and 'irq_nextlevel' public interface. This is a less-than-ideal implementation for the following reasons: 1. SoC main interrupt controller (e.g. GIC) is not a 2nd level interrupt controller; in fact, it is the root interrupt controller and therefore should be treated as such. 2. The only reason for using 'irq_nextlevel' here is to interface Cortex-R arch implementation to the interrupt controller functions. Since there is no nesting or multiple instances of an interrupt controller involved, there is really no point in adding such an abstraction. 3. 2nd level topology adds many unnecessary abstractions and results in strange coding artefacts as well as performance penalty due to additional branching. The solution provided by this commit is as follows: 1. Define a set of SoC layer interrupt management functions (z_soc_irq_*) to be used by the Cortex-R variants that do not have an architecturally specified interrupt controller. 2. Map arch interrupt management functiosn to the SoC layer interrupt management functions (e.g. map 'z_arch_irq_enable' to 'z_soc_irq_enable'). 3. The SoC layer interrupt management functions are implemented by soc/arm/*. If an SoC incorporates a proprietary (not commonly used) interrupt controller, the interrupt management functions can be simply implemented within the SoC layer. If an SoC incorporates a standard interrupt controller such as GIC, these functions can be mapped to the appropriate interrupt controller driver functions either through the 'irq_nextlevel' interface, or a direct driver- specific interface exported by include/drivers/interrupt_controller. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit updates 'xilinx_zynqmp' to use the refactored Cortex-R interrupt system. For more details on the refactored Cortex-R interrupt system, see the PR zephyrproject-rtos#19698. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit updates the Cortex-R port to use the preliminary CMSIS-Core(R) implementation added in the PR zephyrproject-rtos#19964. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit updates the 'xilinx_zynqmp' SoC initialisation code to use the preliminary CMSIS-Core(R) implementation added in the PR zephyrproject-rtos#19964. In addition, it also defines the Core IP revision value for the SoC as specified in the Zynq UltraScale+ Device Technical Reference Manual. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
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Force-pushing to rebase onto the latest master and provide an improved interrupt controller-agnostic implementation of Cortex-R (and to be future AArch32 Cortex-A) arch. |
Here is a quick note on how to test this in qemu_cortex_r5:
Most kernel tests should pass! (without the changes in this PR, many kernel tests will fail due to incorrect interrupt management implementation). Any failing tests, even with this PR, are due to timing instability of QEMU as well as possibly incorrect implementation of Cadence TTC system timer driver (verification required, this should be addressed separately in the future). On a side note, the reason that this currently works without using the correct GIC driver is that the GIC-400 GICv2 driver currently being used is mostly compatible with the PL390 GICv1 (the current driver sets a few extra registers that do not exist on GICv1, but this does not really hinder GIC operation; this is to be addressed in the context of #20217). |
The CMSIS-DSP tests are disabled for the 'qemu_cortex_r5' platform until the Cortex-R architecture port is more mature. This commit should be reverted once the CMSIS-Core(R) integration patches are merged (preliminary work available in zephyrproject-rtos#19698). Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Please rebase and address checkpatch issues. You guys are the experts on this HW but I don't see anything that sticks out to me. |
@stephanosio what is the status of this PR? |
@andrewboie Most of the commits in this PR were separated into smaller PRs for easier reviewing. As for the unmerged commits in this PR, I plan to open separate smaller PRs for them as well, once all the dependencies are merged. |
PR Status
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This PR provides a number of improvements to the existing Cortex-R port.
This PR is part of the preparations for #19644.