Add support for ARMv8-R AArch32 FVP platform #43581
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looks like there is one missing ifdef in irq_manage |
solved |
bbolen
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Mar 9, 2022
povergoing
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March 10, 2022 16:00
Cortex-R52 is an ARMv8-R processor with AArch32 profile. Signed-off-by: Julien Massot <julien.massot@iot.bzh>
The ARMv8-R processors always boot into Hyp mode (EL2) To enter EL1: Program the HACTLR register because it defaults to only allowing EL2 accesses. HACTLR controls whether EL1 can access memory region registers and CPUACTLR. Program the SPSR before entering EL1. Other registers default to allowing accesses at EL1 from reset. Set VBAR to the correct location for the vector table. Set ELR to point to the entry point of the EL1 code and call ERET. Signed-off-by: Julien Massot <julien.massot@iot.bzh>
lib_helpers makes easier to access cp15 based registers, it is inspired from arm64 lib_helpers but use MRC instead of MRS and use cp15 register. Definitions on how to access system registers for AArch32 Armv8 processors can be found in the document: Arm Architecture Reference Manual Armv8, for Armv8-A architecture profile Signed-off-by: Julien Massot <julien.massot@iot.bzh>
This is mostly a copy of the existing arm64 implementation, at the difference that the AArch32 registers do not mention the execution level. Signed-off-by: Julien Massot <julien.massot@iot.bzh>
These definitions are required to be able to use GICv3 interrupts controller on an ARMv8 AArch32 processor. Signed-off-by: Julien Massot <julien.massot@iot.bzh>
This is required by drivers which query the current cpu, at this moment there is no arm aarch32 that use smp, so it seems safe to consider that the current cpu is always the first one. This patch enable the use of the GICv3 driver on ARM 32bits cpu. Signed-off-by: Julien Massot <julien.massot@iot.bzh>
This is mostly the same than the aarch64 one, excepted that we force the armv8r fvp to run in aarch32 profile. So that we can simulate the Cortex-R52. Signed-off-by: Julien Massot <julien.massot@iot.bzh>
I just add the documents for the |
added 2 commits
March 10, 2022 16:13
This board reuse the work did to simulate an ARMv8-R AArch64 profile core using the FVP platform, but use the AArch32 profile. Signed-off-by: Julien Massot <julien.massot@iot.bzh>
On 32bit compiler the BIT_MASK(32) generate a warning, after discussion on zephyrproject-rtos#42226 and zephyrproject-rtos#42163, advise was to use BIT64_MASK instead. Signed-off-by: Julien Massot <julien.massot@iot.bzh>
bbolen
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Mar 10, 2022
No problem, no need to describe ARM DS. |
povergoing
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Mar 11, 2022
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This PR helps to test the Cortex-r52 support provided by #42220.
The fvp_baser_armv8r_aarch32 board is mostly a copy of the
fvp_baser_armv8r present in arm64 bu select the CORTEX_R52 cpu.
Documentation has not been imported since it's the same than fvp_baser_armv8r,
also we rely on the arm64/fvp-aemv8r/fvp-aemv8r.dtsi which can be odd for an arm32
based board.
Tested with FVP_Base_AEMv8R_11.17_21
*** Booting Zephyr OS build zephyr-v3.0.0-644-g08e4612ae972 ***
Hello World! fvp_baser_aemv8r_aarch32