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Add support for ARMv8-R AArch32 FVP platform #43581

Merged
merged 9 commits into from Mar 11, 2022
Merged

Add support for ARMv8-R AArch32 FVP platform #43581

merged 9 commits into from Mar 11, 2022

Commits on Mar 10, 2022

  1. arch: arm: Add support for Cortex-R52 

    Cortex-R52 is an ARMv8-R processor with AArch32 profile.

Signed-off-by: Julien Massot <julien.massot@iot.bzh>
    Julien Massot committed Mar 10, 2022
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  2. arch: arm: cortex_a_r: Add support to start in HYP mode 

    The ARMv8-R processors always boot into Hyp mode (EL2)

To enter EL1:
Program the HACTLR register because it defaults
to only allowing EL2 accesses. HACTLR controls
whether EL1 can access memory region registers and CPUACTLR.
Program the SPSR before entering EL1.
Other registers default to allowing accesses at EL1 from reset.
Set VBAR to the correct location for the vector table.
Set ELR to point to the entry point of the EL1 code and call ERET.

Signed-off-by: Julien Massot <julien.massot@iot.bzh>
    Julien Massot committed Mar 10, 2022
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  3. include: arch: arm: Add Armv8 AArch32 lib_helpers.h 

    lib_helpers makes easier to access cp15 based registers,
it is inspired from arm64 lib_helpers but use
MRC instead of MRS and use cp15 register.

Definitions on how to access system registers for AArch32
Armv8 processors can be found in the document:
Arm Architecture Reference Manual Armv8,
for Armv8-A architecture profile

Signed-off-by: Julien Massot <julien.massot@iot.bzh>
    Julien Massot committed Mar 10, 2022
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  4. arch: arm: aarch32: add ARMv8 timer 

    This is mostly a copy of the existing arm64 implementation,
at the difference that the AArch32 registers do not mention the
execution level.

Signed-off-by: Julien Massot <julien.massot@iot.bzh>
    Julien Massot committed Mar 10, 2022
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  5. arch: arm: cortex_a_r: add MPIDR and SG1R definition 

    These definitions are required to be able to use GICv3
interrupts controller on an ARMv8 AArch32 processor.

Signed-off-by: Julien Massot <julien.massot@iot.bzh>
    Julien Massot committed Mar 10, 2022
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  6. arm: add dummy implementation of arch_curr_cpu 

    This is required by drivers which query the current cpu,
at this moment there is no arm aarch32 that use smp,
so it seems safe to consider that the current cpu is
always the first one.

This patch enable the use of the GICv3 driver on
ARM 32bits cpu.

Signed-off-by: Julien Massot <julien.massot@iot.bzh>
    Julien Massot committed Mar 10, 2022
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  7. soc: arm: add fvp_aemv8r_aarch32 

    This is mostly the same than the aarch64 one, excepted that we
force the armv8r fvp to run in aarch32 profile. So that we can simulate
the Cortex-R52.

Signed-off-by: Julien Massot <julien.massot@iot.bzh>
    Julien Massot committed Mar 10, 2022
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  8. boards: arm: add fvp_baser_armv8r_aarch32 

    This board reuse the work did to simulate an
ARMv8-R AArch64 profile core using the FVP platform,
but use the AArch32 profile.

Signed-off-by: Julien Massot <julien.massot@iot.bzh>
    Julien Massot committed Mar 10, 2022
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  9. drivers: intc_gicv3: use BIT64_MASK instead of BIT_MASK 

    On 32bit compiler the BIT_MASK(32) generate a warning,
after discussion on zephyrproject-rtos#42226 and zephyrproject-rtos#42163, advise was to use
BIT64_MASK instead.

Signed-off-by: Julien Massot <julien.massot@iot.bzh>
    Julien Massot committed Mar 10, 2022
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