Add support for ARMv8-R AArch32 FVP platform

arch/arm/core/aarch32/cortex_a_r/Kconfig

@@ -87,6 +87,13 @@ config CPU_CORTEX_R7
 	help
 	  This option signifies the use of a Cortex-R7 CPU
 
+config CPU_CORTEX_R52
+	bool
+	select CPU_AARCH32_CORTEX_R
+	select AARCH32_ARMV8_R
+	help
+	  This option signifies the use of a Cortex-R52 CPU
+
 if CPU_AARCH32_CORTEX_R
 
 config ARMV7_R
@@ -111,6 +118,19 @@ config ARMV7_R_FP
 	  This option signifies the use of an ARMv7-R processor
 	  implementation supporting the Floating-Point Extension.
 
+config AARCH32_ARMV8_R
+	bool
+	select ATOMIC_OPERATIONS_BUILTIN
+	help
+	  This option signifies the use of an ARMv8-R AArch32 processor
+	  implementation.
+
+	  From https://developer.arm.com/products/architecture/cpu-architecture/r-profile:
+	  The Armv8-R architecture targets at the Real-time profile. It introduces
+	  virtualization at the highest security level while retaining the
+	  Protected Memory System Architecture (PMSA) based on a Memory Protection
+	  Unit (MPU). It supports the A32 and T32 instruction sets.
+
 config ARMV7_EXCEPTION_STACK_SIZE
 	int "Undefined Instruction and Abort stack size (in bytes)"
 	default 256

arch/arm/core/aarch32/cortex_a_r/reset.S

@@ -46,7 +46,40 @@ GTEXT(z_arm_platform_init)
  */
 SECTION_SUBSEC_FUNC(TEXT, _reset_section, z_arm_reset)
 SECTION_SUBSEC_FUNC(TEXT, _reset_section, __start)
+#if defined(CONFIG_AARCH32_ARMV8_R)
+    /* Check if we are starting in HYP mode */
+    mrs r0, cpsr
+    and r0, r0, #MODE_MASK
+    cmp r0, #MODE_HYP
+    bne EL1_Reset_Handler
+
+    /* Init HSCTLR see Armv8-R AArch32 architecture profile */
+    ldr r0, =(HSCTLR_RES1 | SCTLR_I_BIT | SCTLR_C_BIT)
+    mcr p15, 4, r0, c1, c0, 0
+
+    /* Init HACTLR: Enable EL1 access to all IMP DEF registers */
+    ldr r0, =HACTLR_INIT
+    mcr p15, 4, r0, c1, c0, 1
+
+    /* Change EL1 exception base address */
+    ldr r0,=_vector_table
+    mcr p15, 0, r0, c12, c0, 0 /* Write to VBAR */
+
+    /* Go to SVC mode */
+    mrs r0, cpsr
+    bic r0, #MODE_MASK
+    orr r0, #MODE_SVC
+    msr spsr_hyp, r0
+
+    ldr r0, =EL1_Reset_Handler
+    msr elr_hyp, r0
+    dsb
+    isb
+    eret
+
+EL1_Reset_Handler:
 
+#endif
 #if defined(CONFIG_CPU_HAS_DCLS)
     /*
      * Initialise CPU registers to a defined state if the processor is

arch/arm/core/aarch32/cpu_idle.S

@@ -134,6 +134,7 @@ SECTION_FUNC(TEXT, arch_cpu_atomic_idle)
 
 #if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) \
 	|| defined(CONFIG_ARMV7_R) \
+	|| defined(CONFIG_AARCH32_ARMV8_R) \
 	|| defined(CONFIG_ARMV7_A)
 	/* No BASEPRI, call wfe directly
 	 * (SEVONPEND is set in z_arm_cpu_idle_init())

arch/arm/core/aarch32/irq_manage.c

@@ -160,6 +160,7 @@ void _arch_isr_direct_pm(void)
 {
 #if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) \
 	|| defined(CONFIG_ARMV7_R) \
+	|| defined(CONFIG_AARCH32_ARMV8_R) \
 	|| defined(CONFIG_ARMV7_A)
 	unsigned int key;
 
@@ -182,6 +183,7 @@ void _arch_isr_direct_pm(void)
 
 #if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) \
 	|| defined(CONFIG_ARMV7_R) \
+	|| defined(CONFIG_AARCH32_ARMV8_R) \
 	|| defined(CONFIG_ARMV7_A)
 	irq_unlock(key);
 #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)

arch/arm/core/aarch32/isr_wrapper.S

@@ -163,7 +163,8 @@ _idle_state_cleared:
 		/* clear kernel idle state */
 		strne	r1, [r2, #_kernel_offset_to_idle]
 		blne	z_pm_save_idle_exit
-#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A)
+#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_AARCH32_ARMV8_R) \
+	|| defined(CONFIG_ARMV7_A)
 	beq _idle_state_cleared
 	movs r1, #0
 	/* clear kernel idle state */
@@ -252,7 +253,8 @@ spurious_continue:
 	mov lr, r3
 #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
 	pop {r0, lr}
-#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A)
+#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_AARCH32_ARMV8_R) \
+	|| defined(CONFIG_ARMV7_A)
 	/*
 	 * r0 and lr_irq were saved on the process stack since a swap could
 	 * happen.  exc_exit will handle getting those values back

arch/arm/core/aarch32/swap_helper.S

@@ -120,7 +120,8 @@ out_fp_endif:
      * regardless of whether the thread has an active FP context.
      */
 #endif /* CONFIG_FPU_SHARING */
-#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A)
+#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_AARCH32_ARMV8_R) \
+	|| defined(CONFIG_ARMV7_A)
     /* Store rest of process context */
     cps #MODE_SYS
     stm r0, {r4-r11, sp}
@@ -136,7 +137,8 @@ out_fp_endif:
     movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
     msr BASEPRI_MAX, r0
     isb /* Make the effect of disabling interrupts be realized immediately */
-#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A)
+#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_AARCH32_ARMV8_R) \
+	|| defined(CONFIG_ARMV7_A)
     /*
      * Interrupts are still disabled from arch_swap so empty clause
      * here to avoid the preprocessor error below
@@ -344,7 +346,8 @@ in_fp_endif:
     /* load callee-saved + psp from thread */
     add r0, r2, #_thread_offset_to_callee_saved
     ldmia r0, {v1-v8, ip}
-#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A)
+#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_AARCH32_ARMV8_R) \
+	|| defined(CONFIG_ARMV7_A)
 _thread_irq_disabled:
     /* load _kernel into r1 and current k_thread into r2 */
     ldr r1, =_kernel
@@ -602,7 +605,8 @@ valid_syscall_id:
     bx lr
 #endif /* CONFIG_USERSPACE */
 
-#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A)
+#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_AARCH32_ARMV8_R) \
+	|| defined(CONFIG_ARMV7_A)
 
 /**
  *

arch/arm/core/aarch32/thread.c

@@ -563,6 +563,7 @@ void arch_switch_to_main_thread(struct k_thread *main_thread, char *stack_ptr,
 	"movs r1, #0\n\t"
 #if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) \
 	|| defined(CONFIG_ARMV7_R) \
+	|| defined(CONFIG_AARCH32_ARMV8_R) \
 	|| defined(CONFIG_ARMV7_A)
 	"cpsie i\n\t"		/* __enable_irq() */
 #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)

boards/arm/fvp_baser_aemv8r_aarch32/Kconfig.board

@@ -0,0 +1,7 @@
+# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved.
+# Copyright (c) 2022 IoT.bzh
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_FVP_BASER_AEMV8R_AARCH32
+	bool "FVP BaseR AEMv8R AArch32 simulation board"
+	depends on SOC_FVP_AEMV8R_AARCH32

boards/arm/fvp_baser_aemv8r_aarch32/Kconfig.defconfig

@@ -0,0 +1,13 @@
+# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved.
+# Copyright (c) 2022 IoT.bzh
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_FVP_BASER_AEMV8R_AARCH32
+
+config BUILD_OUTPUT_BIN
+	default y
+
+config BOARD
+	default "fvp_baser_aemv8r_aarch32"
+
+endif # BOARD_FVP_BASER_AEMV8R_AARCH32

boards/arm/fvp_baser_aemv8r_aarch32/board.cmake

@@ -0,0 +1,25 @@
+# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved.
+# Copyright (c) 2022 IoT.bzh
+# SPDX-License-Identifier: Apache-2.0
+
+set(SUPPORTED_EMU_PLATFORMS armfvp)
+set(ARMFVP_BIN_NAME FVP_BaseR_AEMv8R)
+
+set(ARMFVP_FLAGS
+  -C cluster0.has_aarch64=0
+  -C cluster0.VMSA_supported=0
+  -C cluster0.NUM_CORES=${CONFIG_MP_NUM_CPUS}
+  -C cluster0.gicv3.cpuintf-mmap-access-level=2
+  -C cluster0.gicv3.SRE-enable-action-on-mmap=2
+  -C cluster0.gicv3.SRE-EL2-enable-RAO=1
+  -C cluster0.gicv3.extended-interrupt-range-support=1
+  -C bp.sram.enable_atomic_ops=1
+  -C gic_distributor.GICD_CTLR-DS-1-means-secure-only=1
+  -C gic_distributor.has-two-security-states=0
+  -C bp.refcounter.non_arch_start_at_default=1
+  -C bp.pl011_uart0.out_file=-
+  -C bp.pl011_uart0.unbuffered_output=1
+  -C bp.terminal_0.start_telnet=0
+  -C bp.vis.disable_visualisation=1
+  -C bp.vis.rate_limit-enable=0
+  )

boards/arm/fvp_baser_aemv8r_aarch32/doc/index.rst

@@ -0,0 +1,96 @@
+.. _fvp_baser_aemv8r_aarch32:
+
+Arm FVP BaseR AEMv8-R AArch32
+#############################
+
+Overview
+********
+
+This board configuration uses Armv8-R AEM FVP [1]_ to emulate a generic
+Armv8-R [2]_ 32-bit hardware platform.
+
+Fixed Virtual Platforms (FVP) are complete simulations of an Arm system,
+including processor, memory and peripherals. These are set out in a
+"programmer's view", which gives you a comprehensive model on which to build
+and test your software.
+
+The Armv8-R AEM FVP is a free of charge Armv8-R Fixed Virtual Platform. It
+supports the latest Armv8-R feature set. Please refer to FVP documentation
+page [3]_ for more details about FVP.
+
+To Run the Fixed Virtual Platform simulation tool you must download "Armv8-R AEM
+FVP" from Arm developer [1]_ (This might require the user to register) and
+install it on your host PC.
+
+Hardware
+********
+
+Supported Features
+==================
+
+The following hardware features are supported:
+
++-----------------------+------------+----------------------+
+| Interface             | Controller | Driver/Component     |
++=======================+============+======================+
+| GICv3                 | on-chip    | interrupt controller |
++-----------------------+------------+----------------------+
+| PL011 UART            | on-chip    | serial port          |
++-----------------------+------------+----------------------+
+| Arm GENERIC TIMER     | on-chip    | system clock         |
++-----------------------+------------+----------------------+
+
+The kernel currently does not support other hardware features on this platform.
+
+When FVP is launched with ``-a, --application FILE`` option, the kernel will be
+loaded into DRAM region ``[0x0-0x7FFFFFFF]``. For more information, please refer
+to the official Armv8-R AEM FVP memory map document [4]_.
+
+Devices
+=======
+
+System Clock
+------------
+
+This board configuration uses a system clock frequency of 100 MHz.
+
+Serial Port
+-----------
+
+This board configuration uses a single serial communication channel with the
+UART0.
+
+Programming and Debugging
+*************************
+
+Use this configuration to build basic Zephyr applications and kernel tests in the
+Arm FVP emulated environment, for example, with the :ref:`synchronization_sample`:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/synchronization
+   :host-os: unix
+   :board: fvp_baser_aemv8r
+   :goals: build
+
+This will build an image with the synchronization sample app. To run with FVP,
+first set environment variable ``ARMFVP_BIN_PATH`` before using it. Then you
+can run it with ``west build -t run``.
+
+.. code-block:: bash
+
+   export ARMFVP_BIN_PATH=/path/to/fvp/directory
+   west build -t run
+
+Debugging
+=========
+
+Refer to the detailed overview about :ref:`application_debugging`.
+
+References
+**********
+
+.. [1] https://developer.arm.com/tools-and-software/simulation-models/fixed-virtual-platforms/arm-ecosystem-models
+.. [2] Arm Architecture Reference Manual Supplement - Armv8, for Armv8-R AArch32 architecture profile
+       https://developer.arm.com/documentation/ddi0568/latest
+.. [3] https://developer.arm.com/tools-and-software/simulation-models/fixed-virtual-platforms/docs
+.. [4] https://developer.arm.com/documentation/100964/1114/Base-Platform/Base---memory/BaseR-Platform-memory-map

boards/arm/fvp_baser_aemv8r_aarch32/fvp_baser_aemv8r_aarch32.dts

@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <arm64/fvp-aemv8r/fvp-aemv8r.dtsi>
+
+/ {
+	model = "FVP BaseR AEMv8R";
+
+	chosen {
+		/*
+		 * The SRAM node is actually located in the
+		 * DRAM region of the FVP BaseR AEMv8R.
+		 */
+		zephyr,sram = &dram0;
+		zephyr,flash = &flash0;
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "hvc";
+		label = "PSCI";
+	};
+
+	soc {
+		flash0: flash@0 {
+			compatible = "soc-nv-flash";
+			reg = <0x0 DT_SIZE_K(64)>;
+		};
+
+		dram0: memory@10000000 {
+			compatible = "mmio-dram";
+			reg = <0x10000000 DT_SIZE_K(2048)>;
+		};
+	};
+};
+
+&uart0 {
+	status = "okay";
+	current-speed = <115200>;
+};

boards/arm/fvp_baser_aemv8r_aarch32/fvp_baser_aemv8r_aarch32.yaml

@@ -0,0 +1,13 @@
+# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved.
+# Copyright (c) 2022 IoT.bzh
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: fvp_baser_aemv8r_aarch32
+name: FVP Emulation FVP_BaseR_AEMv8R AArch32
+arch: arm
+type: sim
+toolchain:
+  - zephyr
+  - cross-compile
+ram: 2048
+flash: 64