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Add support for WCH CH56x series SoC #64472

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@xingrz xingrz commented Oct 27, 2023

QingKe is a series of RISC-V cores developed by WCH, consisting with V2A, V3A and V4B/C/F series of MCUs.

CH569/CH565 are 2 of the members of the QingKe V3A series. This PR brings initial support for these two SoCs to Zephyr.

In summary, this PR includes:

  • An interrupt controller for all QingKe MCUs.
  • A systick driver for the QingKe V3 series.
  • Clock controller and GPIO, UART driver specifically for the CH56x MCUs.
  • Configurations for the official CH565W-EVT and CH569W-EVT evaluation boards

Support for other series members will be submit in future PRs.

References:

TODOs

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Needs to be migrated to hwmv2

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xingrz commented Feb 26, 2024

Needs to be migrated to hwmv2

Yes I'm planning to do that. I'm still waiting for the custom interrupt controller before this PR can go ahead.

@xingrz xingrz force-pushed the wch/pr/ch56x-bringup branch 2 times, most recently from ee192a2 to 1901934 Compare April 11, 2024 03:08
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Colt-Ma commented May 19, 2024

@xingrz @bjarki-trackunit
Is this still progressing? Qingke series microcontrollers will definitely be used in large quantities because of their low price, so I think it is necessary to adapt this series of microcontrollers to zephyr.

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Colt-Ma commented May 19, 2024

@xingrz @bjarki-trackunit
Is this still progressing? Qingke series microcontrollers will definitely be used in large quantities because of their low price, so I think it is necessary to adapt this series of microcontrollers to zephyr.

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xingrz commented May 19, 2024

@xingrz @bjarki-trackunit Is this still progressing? Qingke series microcontrollers will definitely be used in large quantities because of their low price, so I think it is necessary to adapt this series of microcontrollers to zephyr.

Yes, but I'm still waiting for the support for custom interrupt controller #63214 (comment)

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xingrz commented May 20, 2024

@xingrz I will output the uart0 of ch592f as the console, with a baud rate of 115200. However, the actual baud rate seen on the oscilloscope is 114khz. I am not sure where the problem is and how to modify it. I look forward to your prompt. Thank you!

Maybe you need to revert the latest [WIP] TICKLESS] commit from that branch.

We're off-topic. You can contact me from the official Discord.

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xingrz added 14 commits May 23, 2024 14:29
* Website: https://wch-ic.com/

Signed-off-by: Chen Xingyu <hi@xingrz.me>
NOTE: Duplicated with an existing PR. Leaving this commit here just as
a placeholder. Will be rebased soon after that existing PR get merged.

==========================================================================

In certain cases, platforms may have their own implemented interrupt
controllers (e.g., the PFIC on WCH MCUs) that require the ability to
implement the irq_enable/disable functions at the SoC level.

Similar support already exists for ARM and ARM64. This commit adds support
for RISC-V as well.

Signed-off-by: Chen Xingyu <hi@xingrz.me>
QingKe V3 is an RV32IMAC core developed by WCH

Signed-off-by: Chen Xingyu <hi@xingrz.me>
Based on QingKe V3A core, CH569/5 are members of the CH56x series.

Signed-off-by: Chen Xingyu <hi@xingrz.me>
PFIC (Programmable Fast Interrupt Controller) is the interrupt controller
implmentation in WCH QingKe series RISC-V MCUs.

Signed-off-by: Chen Xingyu <hi@xingrz.me>
This driver is shared across QingKe V3A series, including CH32V103,
CH569/5 and CH573/1.

Signed-off-by: Chen Xingyu <hi@xingrz.me>
This commit describes the system control block of the CH56x in DTS. This
block will be utilized in future drivers for functions such as pin
remapping, clock control, and interrupt management.

Additionally, macros has been added to facilitate easy access to the block.

Signed-off-by: Chen Xingyu <hi@xingrz.me>
The CH56x can be configured to run on a 30MHz external oscillator or a
480MHz PLL generated by the USB PHY.

This commit introduces a clock controller that can automatically select
one of the two available clock sources and determine the appropriate
divisor based on the given frequency.

The `CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC` value is also updated with the
selected frequency.

Signed-off-by: Chen Xingyu <hi@xingrz.me>

# Conflicts:
#	drivers/clock_control/Kconfig
#	soc/riscv/riscv-privileged/wch_ch32v/Kconfig.defconfig.ch56x
This commit implements a GPIO driver for CH56x series.

The 2 instances of GPIO share a same IRQ line on this chip. So the config
`SHARED_IRQ` is selected as well.

Signed-off-by: Chen Xingyu <hi@xingrz.me>
This commit introduces a pinctrl driver for the CH5xx series.

The limitations of pin multiplexing of WCH CH5xx series are described
in the binding configuration.

Signed-off-by: Chen Xingyu <hi@xingrz.me>
This commit introduces UART driver for CH5xx series, supporting both polling
and interrupt-driven mode.

Signed-off-by: Chen Xingyu <hi@xingrz.me>
`WCHISPTool_CMD` is the commandline version of WCHISPTool, which is a USB
flashing tool for WCH series MCUs.

Signed-off-by: Chen Xingyu <hi@xingrz.me>
CH565W-EVT and CH569W-EVT are boards by WCH for the evaluation of
CH565W and CH569W chips.

Signed-off-by: Chen Xingyu <hi@xingrz.me>
* Add `WCH Platforms` section
* Add `xingrz` to maintainers of `WCH Platform`

Signed-off-by: Chen Xingyu <hi@xingrz.me>
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10 participants