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Low accuracy on FPGA #8

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shobhitt10 opened this issue Apr 11, 2022 · 2 comments
Open

Low accuracy on FPGA #8

shobhitt10 opened this issue Apr 11, 2022 · 2 comments

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@shobhitt10
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shobhitt10 commented Apr 11, 2022

Hello,
I tried generating bitstreams through cnn.tcl for mnist classification and mean single convolution:
Screenshot (7)

There are no errors in the console apart from few critical clock skew warnings:

image

But, when I use the generated bitstreams, results are very poor:

  • Mean Single convolution

image

  • MNIST Classifcation - low FPGA accuracy

image

Please guide me what am I doing wrong. This is very crucial as I need to accelerate my own cnn for which I am using your work as a reference.

Thanks

@shobhitt10 shobhitt10 reopened this Apr 12, 2022
@shobhitt10 shobhitt10 changed the title Final Block Design Low accuracy on FPGA Apr 12, 2022
@ZhaoqxCN
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The only reason I can imagine is that your clock frequency has been set too high, it should not be higher than 200MHz.

@shobhitt10
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Thanks for replying @ZhaoqxCN

The only reason I can imagine is that your clock frequency has been set too high, it should not be higher than 200MHz.

I checked the clock of zynq PS, it is set as 50MHz (range is 30-60) similar to what is there in PYNQ-CNN.
image

Any other hints?

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