SDRAM controller for MIPSfpga+ system
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readme/misc Delete simulation_log.txt Mar 15, 2017
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src ahb-lite spec signals fixed Sep 25, 2017
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README.md

README.md

ahb_lite_sdram

Simple SDRAM controller for MIPSfpga+ system AHB-Lite bus.

TODO:

Main features:

  • small (~300 rows of code);
  • easy tunable (all time constraints are coded as module params);
  • simple (no clock domain crossing);
  • supports x16 sdram only;
  • only init, read, write and auto-refresh operations;
  • page burst access is not supported;
  • clock suspend mode is not supported;
  • all HSIZE (x32, x16, x8) AHB-Lite data transfer operations supported
  • Micron Technology, Inc. ("MTI") SDRAM Verilog model (v2.3) was used for simulation

[MIPSfpga+ / mipsfpga-plus / MFP] (https://github.com/MIPSfpga/mipsfpga-plus) is a cleaned-up and improved variant of MIPSfpga-based system.