all: rename i386 to x86

doc/langref.html.in

@@ -5126,7 +5126,7 @@ const builtin = @import("builtin");
 const native_arch = builtin.cpu.arch;
 const expect = std.testing.expect;
 
-const WINAPI: std.builtin.CallingConvention = if (native_arch == .i386) .Stdcall else .C;
+const WINAPI: std.builtin.CallingConvention = if (native_arch == .x86) .Stdcall else .C;
 extern "kernel32" fn ExitProcess(exit_code: c_uint) callconv(WINAPI) noreturn;
 
 test "foo" {
@@ -5165,7 +5165,7 @@ export fn sub(a: i8, b: i8) i8 { return a - b; }
 // at link time, when linking statically, or at runtime, when linking
 // dynamically.
 // The callconv specifier changes the calling convention of the function.
-const WINAPI: std.builtin.CallingConvention = if (native_arch == .i386) .Stdcall else .C;
+const WINAPI: std.builtin.CallingConvention = if (native_arch == .x86) .Stdcall else .C;
 extern "kernel32" fn ExitProcess(exit_code: u32) callconv(WINAPI) noreturn;
 extern "c" fn atan2(a: f64, b: f64) f64;
 
@@ -7487,7 +7487,7 @@ volatile (
     : "rcx", "r11"
 );{#end_syntax_block#}
       <p>
-      For i386 and x86_64 targets, the syntax is AT&amp;T syntax, rather than the more
+      For x86 and x86_64 targets, the syntax is AT&amp;T syntax, rather than the more
       popular Intel syntax. This is due to technical constraints; assembly parsing is
       provided by LLVM and its support for Intel syntax is buggy and not well tested.
       </p>
@@ -11608,7 +11608,7 @@ Architectures:
     v5
     v5te
     v4t
-  i386
+  x86
   x86_64 (native)
   xcore
   nvptx
@@ -11687,8 +11687,8 @@ Available libcs:
   arm-linux-gnueabihf
   arm-linux-musleabi
   arm-linux-musleabihf
-  i386-linux-gnu
-  i386-linux-musl
+  x86-linux-gnu
+  x86-linux-musl
   mips64el-linux-gnuabi64
   mips64el-linux-gnuabin32
   mips64el-linux-musl

lib/c.zig

@@ -190,7 +190,7 @@ test "strncmp" {
 // across .o file boundaries. fix comptime @ptrCast of nakedcc functions.
 fn clone() callconv(.Naked) void {
     switch (native_arch) {
-        .i386 => {
+        .x86 => {
             // __clone(func, stack, flags, arg, ptid, tls, ctid)
             //         +8,   +12,   +16,   +20, +24,  +28, +32
             // syscall(SYS_clone, flags, stack, ptid, tls, ctid)

lib/compiler_rt/aulldiv.zig

@@ -7,7 +7,7 @@ const common = @import("common.zig");
 pub const panic = common.panic;
 
 comptime {
-    if (arch == .i386 and abi == .msvc) {
+    if (arch == .x86 and abi == .msvc) {
         // Don't let LLVM apply the stdcall name mangling on those MSVC builtins
         @export(_alldiv, .{ .name = "\x01__alldiv", .linkage = common.linkage });
         @export(_aulldiv, .{ .name = "\x01__aulldiv", .linkage = common.linkage });

lib/compiler_rt/aullrem.zig

@@ -7,7 +7,7 @@ const common = @import("common.zig");
 pub const panic = common.panic;
 
 comptime {
-    if (arch == .i386 and abi == .msvc) {
+    if (arch == .x86 and abi == .msvc) {
         // Don't let LLVM apply the stdcall name mangling on those MSVC builtins
         @export(_allrem, .{ .name = "\x01__allrem", .linkage = common.linkage });
         @export(_aullrem, .{ .name = "\x01__aullrem", .linkage = common.linkage });

lib/compiler_rt/clear_cache.zig

@@ -17,7 +17,7 @@ comptime {
 
 fn clear_cache(start: usize, end: usize) callconv(.C) void {
     const x86 = switch (arch) {
-        .i386, .x86_64 => true,
+        .x86, .x86_64 => true,
         else => false,
     };
     const arm32 = switch (arch) {

lib/compiler_rt/common.zig

@@ -48,7 +48,7 @@ pub const gnu_f16_abi = switch (builtin.cpu.arch) {
     .x86_64,
     => false,
 
-    .i386 => true,
+    .x86 => true,
 
     .arm, .armeb, .thumb, .thumbeb => switch (builtin.abi) {
         .eabi, .eabihf => false,
@@ -79,7 +79,7 @@ pub fn panic(msg: []const u8, error_return_trace: ?*std.builtin.StackTrace, _: ?
 pub const F16T = switch (builtin.cpu.arch) {
     .aarch64, .aarch64_be, .aarch64_32 => f16,
     .riscv64 => if (builtin.zig_backend == .stage1) u16 else f16,
-    .i386, .x86_64 => f16,
+    .x86, .x86_64 => f16,
     else => u16,
 };
 

lib/compiler_rt/divti3.zig

@@ -9,7 +9,7 @@ pub const panic = common.panic;
 comptime {
     if (builtin.os.tag == .windows) {
         switch (arch) {
-            .i386 => {
+            .x86 => {
                 @export(__divti3, .{ .name = "__divti3", .linkage = common.linkage });
             },
             .x86_64 => {

lib/compiler_rt/extendf_test.zig

@@ -140,7 +140,7 @@ test "extendhfsf2" {
     try test__extendhfsf2(0x7f00, 0x7fe00000); // sNaN
     // On x86 the NaN becomes quiet because the return is pushed on the x87
     // stack due to ABI requirements
-    if (builtin.target.cpu.arch != .i386 and builtin.target.os.tag == .windows)
+    if (builtin.target.cpu.arch != .x86 and builtin.target.os.tag == .windows)
         try test__extendhfsf2(0x7c01, 0x7f802000); // sNaN
 
     try test__extendhfsf2(0, 0); // 0

lib/compiler_rt/stack_probe.zig

@@ -30,7 +30,7 @@ comptime {
     }
 
     switch (arch) {
-        .i386,
+        .x86,
         .x86_64,
         => {
             @export(zig_probe_stack, .{ .name = "__zig_probe_stack", .linkage = linkage });
@@ -69,7 +69,7 @@ pub fn zig_probe_stack() callconv(.Naked) void {
                 \\        ret
             );
         },
-        .i386 => {
+        .x86 => {
             // %eax = probe length, %esp = stack pointer
             asm volatile (
                 \\        push   %%ecx
@@ -121,7 +121,7 @@ fn win_probe_stack_only() void {
                 \\         ret
             );
         },
-        .i386 => {
+        .x86 => {
             asm volatile (
                 \\         push   %%ecx
                 \\         push   %%eax
@@ -191,7 +191,7 @@ fn win_probe_stack_adjust_sp() void {
                 \\         ret
             );
         },
-        .i386 => {
+        .x86 => {
             asm volatile (
                 \\         push   %%ecx
                 \\         cmp    $0x1000,%%eax
@@ -243,7 +243,7 @@ pub fn __chkstk() callconv(.Naked) void {
     if (comptime arch.isAARCH64()) {
         @call(.{ .modifier = .always_inline }, win_probe_stack_only, .{});
     } else switch (arch) {
-        .i386 => @call(.{ .modifier = .always_inline }, win_probe_stack_adjust_sp, .{}),
+        .x86 => @call(.{ .modifier = .always_inline }, win_probe_stack_adjust_sp, .{}),
         .x86_64 => @call(.{ .modifier = .always_inline }, win_probe_stack_only, .{}),
         else => unreachable,
     }

lib/ssp.zig

@@ -35,7 +35,7 @@ export fn __chk_fail() callconv(.C) noreturn {
     @panic("buffer overflow detected");
 }
 
-// Emitted when targeting some architectures (eg. i386)
+// Emitted when targeting some architectures (eg. x86)
 // XXX: This symbol should be hidden
 export fn __stack_chk_fail_local() callconv(.C) noreturn {
     __stack_chk_fail();

lib/std/Thread.zig

@@ -753,7 +753,7 @@ const LinuxThreadImpl = struct {
         /// https://github.com/ifduyue/musl/search?q=__unmapself
         fn freeAndExit(self: *ThreadCompletion) noreturn {
             switch (target.cpu.arch) {
-                .i386 => asm volatile (
+                .x86 => asm volatile (
                     \\  movl $91, %%eax
                     \\  movl %[ptr], %%ebx
                     \\  movl %[len], %%ecx
@@ -959,10 +959,10 @@ const LinuxThreadImpl = struct {
             else => |e| return e,
         };
 
-        // Prepare the TLS segment and prepare a user_desc struct when needed on i386
+        // Prepare the TLS segment and prepare a user_desc struct when needed on x86
         var tls_ptr = os.linux.tls.prepareTLS(mapped[tls_offset..]);
-        var user_desc: if (target.cpu.arch == .i386) os.linux.user_desc else void = undefined;
-        if (target.cpu.arch == .i386) {
+        var user_desc: if (target.cpu.arch == .x86) os.linux.user_desc else void = undefined;
+        if (target.cpu.arch == .x86) {
             defer tls_ptr = @ptrToInt(&user_desc);
             user_desc = .{
                 .entry_number = os.linux.tls.tls_image.gdt_entry_number,

lib/std/atomic.zig

@@ -44,7 +44,7 @@ pub inline fn spinLoopHint() void {
         // No-op instruction that can hint to save (or share with a hardware-thread)
         // pipelining/power resources
         // https://software.intel.com/content/www/us/en/develop/articles/benefitting-power-and-performance-sleep-loops.html
-        .i386, .x86_64 => asm volatile ("pause" ::: "memory"),
+        .x86, .x86_64 => asm volatile ("pause" ::: "memory"),
 
         // No-op instruction that serves as a hardware-thread resource yield hint.
         // https://stackoverflow.com/a/7588941

lib/std/build.zig

@@ -2978,12 +2978,12 @@ pub const LibExeObjStep = struct {
                             if (glibc_dir_arg) |dir| {
                                 // TODO look into making this a call to `linuxTriple`. This
                                 // needs the directory to be called "i686" rather than
-                                // "i386" which is why we do it manually here.
+                                // "x86" which is why we do it manually here.
                                 const fmt_str = "{s}" ++ fs.path.sep_str ++ "{s}-{s}-{s}";
                                 const cpu_arch = self.target.getCpuArch();
                                 const os_tag = self.target.getOsTag();
                                 const abi = self.target.getAbi();
-                                const cpu_arch_name: []const u8 = if (cpu_arch == .i386)
+                                const cpu_arch_name: []const u8 = if (cpu_arch == .x86)
                                     "i686"
                                 else
                                     @tagName(cpu_arch);

lib/std/build/EmulatableRunStep.zig

@@ -95,12 +95,12 @@ fn make(step: *Step) !void {
             if (glibc_dir_arg) |dir| {
                 // TODO look into making this a call to `linuxTriple`. This
                 // needs the directory to be called "i686" rather than
-                // "i386" which is why we do it manually here.
+                // "x86" which is why we do it manually here.
                 const fmt_str = "{s}" ++ fs.path.sep_str ++ "{s}-{s}-{s}";
                 const cpu_arch = self.exe.target.getCpuArch();
                 const os_tag = self.exe.target.getOsTag();
                 const abi = self.exe.target.getAbi();
-                const cpu_arch_name: []const u8 = if (cpu_arch == .i386)
+                const cpu_arch_name: []const u8 = if (cpu_arch == .x86)
                     "i686"
                 else
                     @tagName(cpu_arch);

lib/std/c/freebsd.zig

@@ -1444,7 +1444,7 @@ pub const E = enum(u16) {
 };
 
 pub const MINSIGSTKSZ = switch (builtin.cpu.arch) {
-    .i386, .x86_64 => 2048,
+    .x86, .x86_64 => 2048,
     .arm, .aarch64 => 4096,
     else => @compileError("MINSIGSTKSZ not defined for this architecture"),
 };

lib/std/c/netbsd.zig

@@ -80,7 +80,7 @@ pub const pthread_cond_t = extern struct {
 pub const pthread_rwlock_t = extern struct {
     magic: c_uint = 0x99990009,
     interlock: switch (builtin.cpu.arch) {
-        .aarch64, .sparc, .x86_64, .i386 => u8,
+        .aarch64, .sparc, .x86_64, .x86 => u8,
         .arm, .powerpc => c_int,
         else => unreachable,
     } = 0,
@@ -97,15 +97,15 @@ const pthread_spin_t = switch (builtin.cpu.arch) {
     .aarch64, .aarch64_be, .aarch64_32 => u8,
     .mips, .mipsel, .mips64, .mips64el => u32,
     .powerpc, .powerpc64, .powerpc64le => i32,
-    .i386, .x86_64 => u8,
+    .x86, .x86_64 => u8,
     .arm, .armeb, .thumb, .thumbeb => i32,
     .sparc, .sparcel, .sparc64 => u8,
     .riscv32, .riscv64 => u32,
     else => @compileError("undefined pthread_spin_t for this arch"),
 };
 
 const padded_pthread_spin_t = switch (builtin.cpu.arch) {
-    .i386, .x86_64 => u32,
+    .x86, .x86_64 => u32,
     .sparc, .sparcel, .sparc64 => u32,
     else => pthread_spin_t,
 };
@@ -1067,7 +1067,7 @@ pub const ucontext_t = extern struct {
     mcontext: mcontext_t,
     __pad: [
         switch (builtin.cpu.arch) {
-            .i386 => 4,
+            .x86 => 4,
             .mips, .mipsel, .mips64, .mips64el => 14,
             .arm, .armeb, .thumb, .thumbeb => 1,
             .sparc, .sparcel, .sparc64 => if (@sizeOf(usize) == 4) 43 else 8,

lib/std/c/openbsd.zig

@@ -1247,7 +1247,7 @@ pub const E = enum(u16) {
 };
 
 const _MAX_PAGE_SHIFT = switch (builtin.cpu.arch) {
-    .i386 => 12,
+    .x86 => 12,
     .sparc64 => 13,
 };
 pub const MINSIGSTKSZ = 1 << _MAX_PAGE_SHIFT;

lib/std/coff.zig

@@ -1025,7 +1025,7 @@ pub const MachineType = enum(u16) {
             .powerpc => .POWERPC,
             .riscv32 => .RISCV32,
             .thumb => .Thumb,
-            .i386 => .I386,
+            .x86 => .I386,
             .aarch64 => .ARM64,
             .riscv64 => .RISCV64,
             .x86_64 => .X64,
@@ -1040,7 +1040,7 @@ pub const MachineType = enum(u16) {
             .POWERPC => .powerpc,
             .RISCV32 => .riscv32,
             .Thumb => .thumb,
-            .I386 => .i386,
+            .I386 => .x86,
             .ARM64 => .aarch64,
             .RISCV64 => .riscv64,
             .X64 => .x86_64,

lib/std/debug.zig

@@ -182,7 +182,7 @@ pub fn dumpStackTraceFromBase(bp: usize, ip: usize) void {
             // therefore, we do a check for `return_address == 0` before subtracting 1 from it to avoid
             // an overflow. We do not need to signal `StackIterator` as it will correctly detect this
             // condition on the subsequent iteration and return `null` thus terminating the loop.
-            // same behaviour for i386-windows-msvc
+            // same behaviour for x86-windows-msvc
             const address = if (return_address == 0) return_address else return_address - 1;
             printSourceAtAddress(debug_info, stderr, address, tty_config) catch return;
         }
@@ -568,7 +568,7 @@ pub fn writeCurrentStackTrace(
         // therefore, we do a check for `return_address == 0` before subtracting 1 from it to avoid
         // an overflow. We do not need to signal `StackIterator` as it will correctly detect this
         // condition on the subsequent iteration and return `null` thus terminating the loop.
-        // same behaviour for i386-windows-msvc
+        // same behaviour for x86-windows-msvc
         const address = if (return_address == 0) return_address else return_address - 1;
         try printSourceAtAddress(debug_info, out_stream, address, tty_config);
     }
@@ -1922,7 +1922,7 @@ fn handleSegfaultPosix(sig: i32, info: *const os.siginfo_t, ctx_ptr: ?*const any
     }
 
     switch (native_arch) {
-        .i386 => {
+        .x86 => {
             const ctx = @ptrCast(*const os.ucontext_t, @alignCast(@alignOf(os.ucontext_t), ctx_ptr));
             const ip = @intCast(usize, ctx.mcontext.gregs[os.REG.EIP]);
             const bp = @intCast(usize, ctx.mcontext.gregs[os.REG.EBP]);

lib/std/elf.zig

@@ -1502,7 +1502,7 @@ pub const EM = enum(u16) {
             .MIPS_RS3_LE => .mipsel,
             .PPC => .powerpc,
             .SPARC => .sparc,
-            .@"386" => .i386,
+            .@"386" => .x86,
             .XCORE => .xcore,
             .CSR_KALIMBA => .kalimba,
             .LANAI => .lanai,

lib/std/macho.zig

@@ -1201,7 +1201,7 @@ pub const MH_DEAD_STRIPPABLE_DYLIB = 0x400000;
 /// Contains a section of type S_THREAD_LOCAL_VARIABLES
 pub const MH_HAS_TLV_DESCRIPTORS = 0x800000;
 
-/// When this bit is set, the OS will run the main executable with a non-executable heap even on platforms (e.g. i386) that don't require it. Only used in MH_EXECUTE filetypes.
+/// When this bit is set, the OS will run the main executable with a non-executable heap even on platforms (e.g. x86) that don't require it. Only used in MH_EXECUTE filetypes.
 pub const MH_NO_HEAP_EXECUTION = 0x1000000;
 
 /// The code was linked for use in an application extension.
@@ -1444,7 +1444,7 @@ pub const S_ATTR_NO_DEAD_STRIP = 0x10000000;
 /// blocks are live if they reference live blocks
 pub const S_ATTR_LIVE_SUPPORT = 0x8000000;
 
-/// used with i386 code stubs written on by dyld
+/// used with x86 code stubs written on by dyld
 pub const S_ATTR_SELF_MODIFYING_CODE = 0x4000000;
 
 /// section contains some machine instructions