AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining

1. A practical vertex encoding algorithm, which can find a proper set of the neighbor vertex for pattern growth with the consideration of standard cell characteristics, as a part of a high-efficiency FSM solution
2. A pattern growth algorithm that can expand the sizes of gate-level patterns while preserving their high recurrence frequencies. Compared to previous FSM approaches, our pattern growth solution carefully handles the overlaps between pattern subgraphs to meet the technology mapping constraint and maximize area reduction
3. A pattern combination algorithm that can iteratively find a set of gate-level patterns from numerous candidates as the extension part of the initial standard cell library to maximize the area reduction of the entire VLSI design
4. To the best of our knowledge, it is the first automated standard cell extension framework that closes the optimization loop between the analysis of gate-level netlist and standard cell library customization. AutoCellLibX can generate SPICE netlists and GDSII layouts of the custom standard cells for downstream VLSI design flow