This marks the initial release of SonicBOOM (or BOOM v3.0.0). SonicBOOM 3.0.0 can achieve 6.2 CoreMark/MHz..
This is a concurrent release with Chipyard 1.3.
As this is a major BOOM release and update, this release note will summarize both changes since BOOMv2.2.3 (the last versioned release) and BOOMv2.0.0 (the last major release).
Changes since BOOMv2.2.3:
- Cache performance counters (#463)
- TAGE-based branch predictor (#456)
- Support for L0/L1 BTBs (#456)
- Repaired Return-address-stack (#456)
- Superscalar branch resolution (#456)
- Short-forwards-branch internal recoding (#456)
- Automated performance regressions with FireSim (#409)
- Bump to Chipyard 1.3 (#464)
- Fix LSU release search for memory consistency (#448)
- Improve quality of generated Verilog (#449)
- Fix bug with RoCC interface (#437)
Major Changes since BOOMv2.0.0:
- New L1 Cache and LSU with dual-issue loads
- Support for RoCC accelerators
- Refactored issue/rename stages
- Support RVC-extension
- Support PMP registers
- Support breakpoints