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Uart=Stands for Universal Asynchronous Reception and Transmission (UART).A simple serial communication protocol that allows the host communicates with the auxiliary device.UART supports bi-directional, asynchronous and serial data transmission.It has two data lines, one to transmit (TX) and another to receive (RX) which is used to communicate th…
This project implements a SPI (Serial Peripheral Interface) slave module with a single port RAM block. The SPI slave module receives data from a master device and communicates with the single port RAM to store and retrieve data.
This is my HDL code page which I started to showcase my coding skills and documenting my work for future reference. I am pursuing my master's at Texas A&M University (2019-21). I am looking forward to be a verification engineer. If you have any doubts you are welcomed to email me @ arunraja08@gmail.com
RiscV Environment for Simulation (R4VES) is a generic and modular framework that eases the grunt work required in order to perform pre/post-synthesis logic and fault simulation on RISC-V cores based on Model/QuestaSim and Z01X.
This project is focused on the design and verification of digital logic circuits, particularly targeting chip design using Verilog, SystemVerilog, and SVA. The main objectives included designing modules compliant with industry standards such as APB (Advanced Peripheral Bus), memory systems, and systolic matrix multiplication.