Author:
- Alessandro Conti - AlessandroConti11
- De Introna Federico - federicodeintrona
License: MIT license.
Tags: #computer_engineering, #hardware, #memory, #VHDL.
Politecnico di Milano.
Academic Year: 2022/2023.
054441 - Prova Finale (Progetto di Reti Logiche) - professor Fornaciari William.
Implement an hardware module in VHDL that functions as an interface between a memory and four output channels. The module receives serial instructions regarding a memory address and the desired output channel.
The system receives the input data via a single serial bit indicating the memory address from which to retrieve the data and the corresponding output channel. The system outputs consist of four parallel channels that transmit the entire memory word.
Project specifications in full are in the folder: Specification/.
Final Evaluation: 30/30