Popular repositories Loading

1. 6T-SRAM 6T-SRAM Public

   Here is a 6T SRAM design with Schematic and Layout.

   1

2. 8-bit-ALU- 8-bit-ALU- Public

   It is a 8 bit ALU design using CMOS, 90 nm Technology

3. FSM-Asynchronous-Counter FSM-Asynchronous-Counter Public

   It is a Verilog HDL code for a 4-bit FSM Counter .

4. Pipelined-8-bit-RISC-Processor Pipelined-8-bit-RISC-Processor Public

   This is an RTL project on 8 Bit RISC Processor Design using Verilog HDL on FPGA.

   Verilog

5. FSM-Counter-Hardware-Model FSM-Counter-Hardware-Model Public

   It is a RTL Project using Xilinx Vivado Software based on Verilog HDL . It is can be downloaded in a Xilinx FPGA. The operation of the Finite State Machine is explained in the video link below.

   Verilog

6. Automated-Key-Based-Locking-of-Gate-Level-Design-Verification Automated-Key-Based-Locking-of-Gate-Level-Design-Verification Public

   It is a tutorial of Gate-Level Design Obfuscation using Key Gate Locking Technique. Please watch the video for details.

   Verilog