v2.2.6 - Incremental Improvements (attempt 2)

What's Changed

• Feature: Canonicalize register names when parsing, converting e.g. x0 -> zero or fp -> s0.
• Feature: Added support for fcvt.d.w[u] and fcvt.w[u].d instructions
• BugFix: Fixed that registers were treated as UInt32s instead of Int32 (this may have caused subtle bugs before)
• Feature: Added the remainder of the M extension
• BugFix: Fixed a bug in the overflow behavior of mulh
• BugFix: Fix faulty length assertion in jalr

(You can also read the Changelog.md file in this release)

New Contributors

• @superenginegit made their first contribution in #52
• @Joshy-R made their first contribution in #48

Full Changelog: v2.2.5...v2.2.6

v2.2.5 - Emergency Release

2.2.5

• BugFix: Fix missed import in core.simple_instruction

Full Changelog: v2.2.4...v2.2.5

v2.2.4 - Snitch support is getting better

What's Changed

• BugFix: Found and added some missing floating point registers (ft8 to ft11)
• Feature: Add frep support to the snitch emulation
• Feature: Add support for 64-bit floats to the snitch Xssr emulation

Full Changelog: v2.2.3...v2.2.4

v2.2.3 - Flen=64 support and some bugfixes

What's Changed

• Feature: Adding support for 64 bit floating point operations
• BugFix: Fix a bug where -o libc would fail with packaged versions of riscemu
• BugFix: Fix __all__ to now properly work (use name strings instead of values)

Full Changelog: v2.2.2...v2.2.3

v2.2.2 - Pyright makes everyone happy!

Changes:

• Dev: Add __all__ to riscemu.{core,instructions,decoder} modules to make pyright in other projects happy
• Perf: very minor fix related to not converting values twice when loaded from memory

Full Changelog: v2.2.1...v2.2.2

v2.1.1 - Finally publishing in CI?

This is a release to test if pythonpublish.yml works now. :/

v2.2.0 - A whole new core

What's Changed

• Feature: Added Zicsr extension and with that support for CSRs
• Feature: Starting to add support for Snitch architecture (Xssr)
• Feature: Add support for .p2align assembler directive
• Rework: Improve handling of immediates, so that beq a0, a1, 1b and beq a0, a1, -16 can both can be handled correctly.
• BugFix: Fix some more errors in the RV32F implementation
• Dev: Move to poetry for project development environment
• Dev: Module refactoring, core datastructures now mostly live inside riscemu.core
• Perf: Improved performance by around 1.8x

New Contributors

• @kianmeng made their first contribution in #45

Full Changelog: v2.1.1...v2.2.0

v2.1.1 - Bugfixes Galore

What's Changed

• Fix formatting issues for CI by @adutilleul in #28
• Fix some issues in the RV32F extension implementation by @adutilleul in #27
• Allow for infinite registers in sw/lw instructions by @superlopuh in #31
• Debugger fix by @KGrykiel in #32

New Contributors

• @adutilleul made their first contribution in #28
• @KGrykiel made their first contribution in #32

Full Changelog: v2.1.0...v2.1.1

2.1.0 Adding float support and making API friendlier

Changes:

• Added a very basic libc containing a crt0.s, and a few functions such as malloc, rand, and memcpy.
• Added a subset of the mmap2 syscall (code 192) to allocate new memory
• Refactored the launching code to improve using riscemu from code
• Added an option to start with the provided libc: -o libc
• Added floating point support (enabled by default). The RV32F extension is now available

2.0.4

Bugfixes:

• Fix an issue with sign handling for rd rs rs type instructions
• Respect conf.debug_instruction = False to supress debug instructions