Design and implementation of a 5-bit pattern recognizer on a Cyclone series FPGA.
Specifications:
- Synchronous system
- Asynchronous reset
- The pattern is "11100"
- It uses two 7-segments display
- After more than 99 pattern occurances the displays show "--"
- The reset button intialize the counters to "00".
Project part of the course Design of Digital Systems , UTwente , 2019
Design of a testable description of the pattern recongnizer and a testbench for functionality testing.
Based on the behavioral design create a hierarchical design with a top-level entity and components having the same functionality with the behavioral design.
Design of a golden unit for automated testing between the behavioral and the structural description.
After the synthesis and the timimg constraints create a post-simulation file and test it in the golden unit against the behavioral and the structural description.