Pinned Loading

1. RISC-X RISC-X Public

   A simple pipelined RISC-V core.

   SystemVerilog 3 3

2. julia_to_uvm_verification julia_to_uvm_verification Public

   Forked from KelvinVale/julia_to_uvm_verification

   It is a Julia script that generates VIP for interfaces, test file and top file in SystemVerilog.

   Julia

3. SystemVerilog_Playground SystemVerilog_Playground Public

   This is where I put the SystemVerilog codes I made that I find the most interesting.

   SystemVerilog 1

4. riscv-formal riscv-formal Public

   Forked from YosysHQ/riscv-formal

   RISC-V Formal Verification Framework

   Verilog 1

5. FFT-Module-Verification FFT-Module-Verification Public

   This is a UVM testbench for the functional verification of a FFT module.

   SystemVerilog 2