Gated clocks in classic.

[rossc719g]

I've got a pretty complicated design built in classic. And the other day, a decision came down that we will be using it with a gated clock (For thermal, di/dt, and other reasons). This would not be an issue, except that the design requires that everything uses the gated clock except for one specific bit deep in the module hierarchy which needs to use the ungated clock.

Using bsv2bsc I was able to get this syntax:

{-# properties mkFoo = { gate_input_clocks [default_clock],
                         clock_ancestors [[nogateClk,default_clock]] } #-}

But, it seems that this syntax is purely aspirational, and is not actually supported (See issue #224).

I fear that my options are pretty limited here, but before I resign myself to one of the following "bad options", I thought I might ask: Does anyone have any clever ideas on how to do this in a better/cleaner way?

Bad options I have thought of:

• Rewrite everything in .bsv. (Badness level is 11/10)
• Just quietly pass an already gated clk for the top level of my module without bluespec being aware of it, and then pass in the ungated clock as an argument down to the module that needs it, and use something like a mkNullCrossingWire to sweep it all under the rug knowing that it is actually safe, even though I am doing it in a way that seems unsafe. (This is relatively easy, but still feels stinky, with a Badness of about 5/10)
• Add the required pragmas for classic. (Badness level is 9/10 for me, but probably only 3/10 for @nanavati, who would end up being the victim at the end of the day)

[quark17]

The third option (add the pragmas to BSC) is the way to go, and it should be almost trivial. Everything after the parser already handles the pragma, and the BH parser already handles attributes on modules, it's just that the BH parser hardcodes which attributes it allows. Supporting gate_input_clocks, for example, requires just one line to be added to pProp inside pPragma (here in the source), such as:

||! literal (mkFString "gate_input_clocks") ..+ eq ..+ l L_lcurl ..+ sepBy varcon cm +.. l L_rcurl >>- PPgate_input_clocks

The above line parses curly braces for the list, so it would accept the following syntax:

{-# properties mkTest = { verilog,
                          gate_input_clocks = { default_clock } } #-}

We could use square brackets (with or without an equal sign), but I notice that none of the other attributes use square brackets and they all have equal signs, so I stuck with the existing style.

Incidentally, I notice that synthesize can be used in place of verilog, but only in one of the two ways to specify it:

{-# verilog mkTest #-}  -- supported
{-# synthesize mkTest #-}  -- supported

{-# properties mkTest = { verilog } #-}  -- supported
{-# properties mkTest = { synthesize } #-}  -- not supported

This, too, can be fixed by adding just one line to pProp:

||! l L_synthesize .> PPverilog

As for your second option, I'm not sure I understand what is being proposed. But I don't think that matters, since option 3 is both the right thing and easy to do. Deciding what syntax we want and then writing tests for the testsuite are probably the hardest parts. And cleaning up the pretty-printer to match whatever syntax we create, and perhaps add tests for that (in the parse-print-parse tests).

[rossc719g]

Thanks!
I think we are going to go with your suggestion and add the pragmas to the classic parser.
This info should be pretty helpful in doing that, I appreciate it!

[rossc719g]

I believe this is now fixed by #624 (and #626), though I have not had a moment to try it out yet.

Does anyone see anything else here that is still open?