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clk: amlogic: introduce a common pclk definition
All Amlogic peripheral clocks are more or less the same. The only thing that differs is the parent data. Adapt the common pclk definition so it takes clk_parent_data and can be used by all controllers. Reviewed-by: Chuan Liu <chuan.liu@amlogic.com> Link: https://lore.kernel.org/r/20250825-meson-clk-cleanup-24-v2-8-0f402f01e117@baylibre.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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+54
-33
lines changed

7 files changed

+54
-33
lines changed

‎drivers/clk/meson/a1-peripherals.c‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1840,8 +1840,10 @@ static struct clk_regmap a1_cecb_32k_out = {
18401840
},
18411841
};
18421842

1843+
static const struct clk_parent_data a1_pclk_parents = { .hw = &a1_sys.hw };
1844+
18431845
#define A1_PCLK(_name, _reg, _bit, _flags) \
1844-
MESON_PCLK(a1_##_name, _reg, _bit, &a1_sys.hw, _flags)
1846+
MESON_PCLK(a1_##_name, _reg, _bit, &a1_pclk_parents, _flags)
18451847

18461848
/*
18471849
* NOTE: The gates below are marked with CLK_IGNORE_UNUSED for historic reasons

‎drivers/clk/meson/axg.c‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1915,8 +1915,10 @@ static struct clk_regmap axg_gen_clk = {
19151915
},
19161916
};
19171917

1918+
static const struct clk_parent_data axg_pclk_parents = { .hw = &axg_clk81.hw };
1919+
19181920
#define AXG_PCLK(_name, _reg, _bit, _flags) \
1919-
MESON_PCLK(axg_##_name, _reg, _bit, &axg_clk81.hw, _flags)
1921+
MESON_PCLK(axg_##_name, _reg, _bit, &axg_pclk_parents, _flags)
19201922

19211923
/*
19221924
* Everything Else (EE) domain gates

‎drivers/clk/meson/g12a.c‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4384,11 +4384,13 @@ static struct clk_regmap sm1_nna_core_clk = {
43844384
},
43854385
};
43864386

4387+
static const struct clk_parent_data g12a_pclk_parents = { .hw = &g12a_clk81.hw };
4388+
43874389
#define G12A_PCLK(_name, _reg, _bit, _flags) \
4388-
MESON_PCLK(_name, _reg, _bit, &g12a_clk81.hw, _flags)
4390+
MESON_PCLK(_name, _reg, _bit, &g12a_pclk_parents, _flags)
43894391

43904392
#define G12A_PCLK_RO(_name, _reg, _bit, _flags) \
4391-
MESON_PCLK_RO(_name, _reg, _bit, &g12a_clk81.hw, _flags)
4393+
MESON_PCLK_RO(_name, _reg, _bit, &g12a_pclk_parents, _flags)
43924394

43934395
/*
43944396
* Everything Else (EE) domain gates

‎drivers/clk/meson/gxbb.c‎

Lines changed: 17 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -2721,8 +2721,10 @@ static struct clk_regmap gxbb_gen_clk = {
27212721
},
27222722
};
27232723

2724+
static const struct clk_parent_data gxbb_pclk_parents = { .hw = &gxbb_clk81.hw };
2725+
27242726
#define GXBB_PCLK(_name, _reg, _bit, _flags) \
2725-
MESON_PCLK(_name, _reg, _bit, &gxbb_clk81.hw, _flags)
2727+
MESON_PCLK(_name, _reg, _bit, &gxbb_pclk_parents, _flags)
27262728

27272729
/*
27282730
* Everything Else (EE) domain gates
@@ -2817,14 +2819,20 @@ static GXBB_PCLK(gxbb_ao_iface, HHI_GCLK_AO, 3, CLK_IGNORE_UNUSED);
28172819
static GXBB_PCLK(gxbb_ao_i2c, HHI_GCLK_AO, 4, CLK_IGNORE_UNUSED);
28182820

28192821
/* AIU gates */
2820-
static MESON_PCLK(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6, &gxbb_aiu.hw, CLK_IGNORE_UNUSED);
2821-
static MESON_PCLK(gxbb_iec958, HHI_GCLK_MPEG1, 7, &gxbb_aiu_glue.hw, CLK_IGNORE_UNUSED);
2822-
static MESON_PCLK(gxbb_i2s_out, HHI_GCLK_MPEG1, 8, &gxbb_aiu_glue.hw, CLK_IGNORE_UNUSED);
2823-
static MESON_PCLK(gxbb_amclk, HHI_GCLK_MPEG1, 9, &gxbb_aiu_glue.hw, CLK_IGNORE_UNUSED);
2824-
static MESON_PCLK(gxbb_aififo2, HHI_GCLK_MPEG1, 10, &gxbb_aiu_glue.hw, CLK_IGNORE_UNUSED);
2825-
static MESON_PCLK(gxbb_mixer, HHI_GCLK_MPEG1, 11, &gxbb_aiu_glue.hw, CLK_IGNORE_UNUSED);
2826-
static MESON_PCLK(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12, &gxbb_aiu_glue.hw, CLK_IGNORE_UNUSED);
2827-
static MESON_PCLK(gxbb_adc, HHI_GCLK_MPEG1, 13, &gxbb_aiu_glue.hw, CLK_IGNORE_UNUSED);
2822+
static const struct clk_parent_data gxbb_aiu_glue_parents = { .hw = &gxbb_aiu.hw };
2823+
static MESON_PCLK(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6, &gxbb_aiu_glue_parents, CLK_IGNORE_UNUSED);
2824+
2825+
static const struct clk_parent_data gxbb_aiu_pclk_parents = { .hw = &gxbb_aiu_glue.hw };
2826+
#define GXBB_AIU_PCLK(_name, _bit, _flags) \
2827+
MESON_PCLK(_name, HHI_GCLK_MPEG1, _bit, &gxbb_aiu_pclk_parents, _flags)
2828+
2829+
static GXBB_AIU_PCLK(gxbb_iec958, 7, CLK_IGNORE_UNUSED);
2830+
static GXBB_AIU_PCLK(gxbb_i2s_out, 8, CLK_IGNORE_UNUSED);
2831+
static GXBB_AIU_PCLK(gxbb_amclk, 9, CLK_IGNORE_UNUSED);
2832+
static GXBB_AIU_PCLK(gxbb_aififo2, 10, CLK_IGNORE_UNUSED);
2833+
static GXBB_AIU_PCLK(gxbb_mixer, 11, CLK_IGNORE_UNUSED);
2834+
static GXBB_AIU_PCLK(gxbb_mixer_iface, 12, CLK_IGNORE_UNUSED);
2835+
static GXBB_AIU_PCLK(gxbb_adc, 13, CLK_IGNORE_UNUSED);
28282836

28292837
/* Array of all clocks provided by this provider */
28302838

‎drivers/clk/meson/meson-clkc-utils.h‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,7 @@ struct meson_clkc_data {
2727
int meson_clkc_syscon_probe(struct platform_device *pdev);
2828
int meson_clkc_mmio_probe(struct platform_device *pdev);
2929

30-
#define __MESON_PCLK(_name, _reg, _bit, _ops, _pname, _flags) \
30+
#define __MESON_PCLK(_name, _reg, _bit, _ops, _pdata, _flags) \
3131
struct clk_regmap _name = { \
3232
.data = &(struct clk_regmap_gate_data) { \
3333
.offset = (_reg), \
@@ -36,16 +36,16 @@ struct clk_regmap _name = { \
3636
.hw.init = &(struct clk_init_data) { \
3737
.name = #_name, \
3838
.ops = _ops, \
39-
.parent_hws = (const struct clk_hw *[]) { _pname }, \
39+
.parent_data = (_pdata), \
4040
.num_parents = 1, \
4141
.flags = (_flags), \
4242
}, \
4343
}
4444

45-
#define MESON_PCLK(_name, _reg, _bit, _pname, _flags) \
46-
__MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ops, _pname, _flags)
45+
#define MESON_PCLK(_name, _reg, _bit, _pdata, _flags) \
46+
__MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ops, _pdata, _flags)
4747

48-
#define MESON_PCLK_RO(_name, _reg, _bit, _pname, _flags) \
49-
__MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pname, _flags)
48+
#define MESON_PCLK_RO(_name, _reg, _bit, _pdata, _flags) \
49+
__MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pdata, _flags)
5050

5151
#endif

‎drivers/clk/meson/meson8b.c‎

Lines changed: 18 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -2701,8 +2701,10 @@ static struct clk_regmap meson8b_cts_i958 = {
27012701
},
27022702
};
27032703

2704+
static const struct clk_parent_data meson8b_pclk_parents = { .hw = &meson8b_clk81.hw };
2705+
27042706
#define MESON8B_PCLK(_name, _reg, _bit, _flags) \
2705-
MESON_PCLK(_name, _reg, _bit, &meson8b_clk81.hw, _flags)
2707+
MESON_PCLK(_name, _reg, _bit, &meson8b_pclk_parents, _flags)
27062708

27072709
/*
27082710
* Everything Else (EE) domain gates
@@ -2785,18 +2787,21 @@ static MESON8B_PCLK(meson8b_vclk2_other, HHI_GCLK_OTHER, 26, CLK_IGNORE_UNUSED);
27852787
static MESON8B_PCLK(meson8b_edp, HHI_GCLK_OTHER, 31, CLK_IGNORE_UNUSED);
27862788

27872789
/* AIU gates */
2788-
static MESON_PCLK(meson8b_aiu_glue, HHI_GCLK_MPEG1, 6, &meson8b_aiu.hw, CLK_IGNORE_UNUSED);
2789-
2790-
#define MESON_AIU_PCLK(_name, _reg, _bit, _flags) \
2791-
MESON_PCLK(_name, _reg, _bit, &meson8b_aiu_glue.hw, _flags)
2792-
2793-
static MESON_AIU_PCLK(meson8b_iec958, HHI_GCLK_MPEG1, 7, CLK_IGNORE_UNUSED);
2794-
static MESON_AIU_PCLK(meson8b_i2s_out, HHI_GCLK_MPEG1, 8, CLK_IGNORE_UNUSED);
2795-
static MESON_AIU_PCLK(meson8b_amclk, HHI_GCLK_MPEG1, 9, CLK_IGNORE_UNUSED);
2796-
static MESON_AIU_PCLK(meson8b_aififo2, HHI_GCLK_MPEG1, 10, CLK_IGNORE_UNUSED);
2797-
static MESON_AIU_PCLK(meson8b_mixer, HHI_GCLK_MPEG1, 11, CLK_IGNORE_UNUSED);
2798-
static MESON_AIU_PCLK(meson8b_mixer_iface, HHI_GCLK_MPEG1, 12, CLK_IGNORE_UNUSED);
2799-
static MESON_AIU_PCLK(meson8b_adc, HHI_GCLK_MPEG1, 13, CLK_IGNORE_UNUSED);
2790+
static const struct clk_parent_data meson8b_aiu_glue_parents = { .hw = &meson8b_aiu.hw };
2791+
static MESON_PCLK(meson8b_aiu_glue, HHI_GCLK_MPEG1, 6,
2792+
&meson8b_aiu_glue_parents, CLK_IGNORE_UNUSED);
2793+
2794+
static const struct clk_parent_data meson8b_aiu_pclk_parents = { .hw = &meson8b_aiu_glue.hw };
2795+
#define MESON8B_AIU_PCLK(_name, _bit, _flags) \
2796+
MESON_PCLK(_name, HHI_GCLK_MPEG1, _bit, &meson8b_aiu_pclk_parents, _flags)
2797+
2798+
static MESON8B_AIU_PCLK(meson8b_iec958, 7, CLK_IGNORE_UNUSED);
2799+
static MESON8B_AIU_PCLK(meson8b_i2s_out, 8, CLK_IGNORE_UNUSED);
2800+
static MESON8B_AIU_PCLK(meson8b_amclk, 9, CLK_IGNORE_UNUSED);
2801+
static MESON8B_AIU_PCLK(meson8b_aififo2, 10, CLK_IGNORE_UNUSED);
2802+
static MESON8B_AIU_PCLK(meson8b_mixer, 11, CLK_IGNORE_UNUSED);
2803+
static MESON8B_AIU_PCLK(meson8b_mixer_iface, 12, CLK_IGNORE_UNUSED);
2804+
static MESON8B_AIU_PCLK(meson8b_adc, 13, CLK_IGNORE_UNUSED);
28002805

28012806
/* Always On (AO) domain gates */
28022807

‎drivers/clk/meson/s4-peripherals.c‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3165,8 +3165,10 @@ static struct clk_regmap s4_gen_clk = {
31653165
},
31663166
};
31673167

3168+
static const struct clk_parent_data s4_pclk_parents = { .hw = &s4_sys_clk.hw };
3169+
31683170
#define S4_PCLK(_name, _reg, _bit, _flags) \
3169-
MESON_PCLK(_name, _reg, _bit, &s4_sys_clk.hw, _flags)
3171+
MESON_PCLK(_name, _reg, _bit, &s4_pclk_parents, _flags)
31703172

31713173
/*
31723174
* NOTE: The gates below are marked with CLK_IGNORE_UNUSED for historic reasons

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