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@C-L-G

Chinese-Logic-Group

FPGA中国开源组织

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  1. My_Opensource_AZPR_SOC My_Opensource_AZPR_SOC Public

    根据最近看的一本书编写的对应RTL以及Testbench

    Verilog 19 9

  2. video_timing_generator video_timing_generator Public

    标准视频时序生成器

    Verilog 9 3

  3. sort sort Public

    排序 verilog 实现

    Verilog 8 8

  4. AXI_BFM AXI_BFM Public

    AXI 总线验证 模块

    SystemVerilog 8 3

  5. altera_vdma_ddr altera_vdma_ddr Public

    altera video DMA

    Verilog 8 5

  6. RGB-YCbCr RGB-YCbCr Public

    RGB 和 YCbCr 高精度互转

    Verilog 6 6

Repositories

Showing 10 of 40 repositories
  • RHDL Public

    尝试构造新的硬件描述语言

    C-L-G/RHDL’s past year of commit activity
    Ruby 0 GPL-3.0 0 0 0 Updated Feb 9, 2020
  • mentor_auto_script Public

    auto_generate script of TCL for modelsim

    C-L-G/mentor_auto_script’s past year of commit activity
    Ruby 2 GPL-3.0 1 0 0 Updated Feb 9, 2020
  • stream-to-file-package Public

    把数据流输出到文件

    C-L-G/stream-to-file-package’s past year of commit activity
    SystemVerilog 4 GPL-3.0 1 0 0 Updated Feb 9, 2020
  • AXI_BFM Public

    AXI 总线验证 模块

    C-L-G/AXI_BFM’s past year of commit activity
    SystemVerilog 8 GPL-3.0 3 0 0 Updated Feb 9, 2020
  • FIFO_HDL Public

    mini FIFO verilog script

    C-L-G/FIFO_HDL’s past year of commit activity
    SystemVerilog 0 GPL-3.0 0 0 0 Updated Feb 9, 2020
  • altera_vdma_ddr Public

    altera video DMA

    C-L-G/altera_vdma_ddr’s past year of commit activity
    Verilog 8 GPL-3.0 5 0 0 Updated Feb 9, 2020
  • video_timing_generator Public

    标准视频时序生成器

    C-L-G/video_timing_generator’s past year of commit activity
    Verilog 9 GPL-3.0 3 0 0 Updated Feb 9, 2020
  • scripts Public

    脚本参考，包括shell perl tcl等

    C-L-G/scripts’s past year of commit activity
    Perl 1 1 1 0 Updated May 6, 2019
  • SPI_configure_registers Public

    通过spi配置寄存器

    C-L-G/SPI_configure_registers’s past year of commit activity
    SystemVerilog 1 GPL-3.0 1 0 0 Updated Mar 26, 2017
  • My_Opensource_AZPR_SOC Public

    根据最近看的一本书编写的对应RTL以及Testbench

    C-L-G/My_Opensource_AZPR_SOC’s past year of commit activity
    Verilog 19 Apache-2.0 9 1 0 Updated Mar 12, 2017
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