Need to rework the entire DRC architecture to only work on the final features that are generated and also be able to easily extend the rules that would be used to verify the chip design. Ideally this would include a mechanism that would allow designer to generate rule scripts that would be used to extend the DRC capability without having to write code.

The current DRC accepts very few rules and basically drives the entire algorithm. We need to have a more comprehensive DRC and make that work at different levels of abstraction.

Levels:
Technology – wire width, spacing, component/feature spacing
Functional – TBD Microfluidic Functionality
Design Methodology – Clustering , hierarchy depth, etc. in Analog VLSI.
Commercial – Number of layers, chip area

The technology levels themselves will have multiple levels of DRC that need to be run.