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RISC (Reduced Instruction Set Computer) was first initiated by John Cocke, a researcher from IBM in Yorktown, New York in 1974 when he proved that about 20% of the instructions on a processor actually handle about 80% of its work. The first computer to use this RISC concept was the IBM PC/XT in the 1980s. The term RISC itself was first popularized by David Patterson, a lecturer at the University of California at Berkeley.
RISC is a computer architecture or modern computing architecture with the simplest instructions and execution types. This architecture is used in high-performance computers, such as vector computers. Besides being used in vector computers, this design is also implemented in other computer processors, such as in some Intel 960 microprocessors, Itanium (IA64) from Intel Corporation, Alpha AXP from DEC, R4x00 from MIPS Corporation, PowerPC and POWER architecture from International Business Machine. In addition, RISC is also commonly used in Advanced RISC Machine (ARM) and StrongARM (including Intel XScale), SPARC and UltraSPARC from Sun Microsystems, and PA-RISC from Hewlett-Packard.
RISC VS CISC
History of RISC-V RISC-V is a free, open-source instruction set architecture based on RISC principles. As an ISA fixed specification, designers can build their own implementations.
RISC-V was launched in 2010 at the University of California at Berkeley Par Lab Project, a simple, efficient, and extensible instruction set architecture, and has no restrictions on sharing.
The first milestone in the RISC-V timeline was the publication of the first project paper entitled "The RISC-V Instruction Set Manual, Volume 1: Base User-Level ISA" in May 2011. The same year saw another major milestone: the first tape-out of a RISC-V chip. The chip, on 28nm FDSOI, was donated by STMicroelectronics and served as a proof of concept for the project.
In 2014, RISC-V published a paper on The Benefits of Open Instruction.
In January 2015, RISC-V held its first workshop. And in the same year also established the RISC-V foundation to maintain RISC-V and with 36 founding members. With the goal of building an open and collaborative community of software and hardware innovators based on RISC-V ISA.
Three years after the founding of the RISC-V Foundation, the popularity of RISC-V continues to increase. In 2018 the Foundation announced a collaboration with the Linux Foundation. This step is very important for RISC-V, as the Linux Foundation, based on its successful and long-standing history, provides operational, technical, and strategic support for RISC-V.
Throughout 2018 to 2019, the RISC-V community has reflected the geo-political landscape and we have heard concerns from around the world that investment in RISC-V must be accompanied by continuity of IP access to ensure long-term strategic investment. We first mentioned our intention to move at the December 2018 summit. The incorporation in Switzerland had the effect of calming fears of political interference with the open collaboration model. RISC-V International does not maintain commercial interests in products or services as a non-profit membership organization. There have been no export restrictions on RISC-V in the US and we have complied with all US laws. This move does not circumvent existing restrictions, but rather reduces uncertainty going forward.
In March 2020, the RISC-V International Association was established in Switzerland. Alongside this, we moved to a new, more inclusive membership structure. RISC-V International members have access to and participate in the development of ISA RISC-V specifications and extensions as well as related hardware and software. RISC-V has a Board of Directors consisting of member representatives as well as a Technical Committee of working group leaders.
Most of the laptops, desktops and servers are based on X86 or AMD64 ISA. IP belongs to Intel and AMD.
Most mobile phones and tablets are based on ARM ISA, IP is divided into A series, R series, and M series.
While RISC-V is very suitable for use in some specific application areas such as storage, edge computing, and AI applications. So RISC-V, ARM, and x86 are in different application fields. And here are some advantages of RISC-V compared to ARM and X86:
Free: RISC-V is open-source, no need to pay for IP.
Simple: RISC-V is much smaller than other commercial SPAs.
Modular: RISC-V has a small standard ISA base, with some standard extensions.
Stable: The base and the first standard extension are already frozen. No need to worry about major updates.
Possibility to extend: Specific functions can be added based on extensions. There are many more extensions in development, such as Vector.
RISC-V uses a standard naming convention to describe the ISAs supported in a given implementation ISA Name format: RV[###][abv....xyz]
RV- Indicates a RISC-V architecture [###]-[32,64,128] Indicate the width of the integer register file and the size of the user address space
[abc...xyz] -Used to Indicate the set of extensions supported by an implementation
Extensions define instructions
-
Ifor Integer is the only required extension is a RISC-V -
The RISC-V specification defines a number of
Standard Extensions -
RISC-V allows
Non-Standardextensions for an implementation
RVWMO = Weak Memory Ordering
RV32I = Base Integer Instruction Set, 32-bit
RV32E = Base Integer Instruction Set (embedded), 32-bit, 16 registers
RV64I = Base Integer Instruction Set, 64-bit
RV128I = Base Integer Instruction Set, 128-bit
I Integer
M Integer Multiplication and Division
A Atomics
F Single-Precision Floating Point
D Double-Precision Floating Point
G General Purpose IMAFD
C 16-bit Compressed Instructions
Xext Non-standard extension
six instruction formats for RISC-V, as follows
RISC-V defines an exact order that must be used to define the RISC-V ISA subset:
RV [32, 64, 128] `` I, M, A, F, D, G, Q, L, C, B, J, T, P, V, N
For example, RV32IMAFDQC is legal, whereas RV32IMAFDCQ is not.
RISC-V Privilege levels
Machine(M-mode) - Berkeley BootLoader (BBL)
Hypervisor(H-mode) - September 2017
Supervisor(S-mode) - OS kernel
User(U-mode) -.sbin/init
M
Simple embedded
M, U
Simple embedded with protection
M, S, U
UNIX like OS(FreeBSD,Linux)
RISC-V is really unique because it is a common, free, open-source ISA to which software can be ported, hardware can be developed, enables innovation and has a great community, can accelerate the development of open computing architectures specifically designed for the Big Data environment and processors can be built to support it.
After explaining all about RISC (Reduced Instruction Set Architecture) and introducing the important characteristics that distinguish RISC from CISC designs. The CISC design provides complex instructions and a large number of modes addressed. The reason for this complexity is the desire to close the semantic gap that exists between high-level languages and machine languages. Initially, the effective use of processor and memory resources is very urgent. Complex instructions tend to minimize requirements memory.
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