Peter Cheung, V1.0 - 2 Nov 2022
By the end of this experiment, you should be able to:
- design and test a PRBS (Pseudo Random Binary Sequence) generator using a linear feedback shift register (LFSR)
- display 8-bit value on neopixel bar on Vbuddy
- specify a FSM (Finite State Machine) in SystemVerilog
- design a FSM to cycle through the Formula 1 starting light sequence
- understand how the clktick.sv module works, and calibrate it for 1 sec tick period
- automatically cycle through F1 lights at 1 second interval
- optionally implement the full F1 starting light machine and test your reaction. - task 4 (massive)
Clone this repo to your local disk. Note that Vbuddy.cpp file in this repo is new and is version 1.1.