Pinned Loading

1. 16-bit_RISC_Processor 16-bit_RISC_Processor Public

   Verilog 1

2. 5-port_NoC_Router 5-port_NoC_Router Public

   SystemVerilog 1

3. Image_Processing_in_Verilog Image_Processing_in_Verilog Public

   Verilog 1

4. Pipeline_Simulator Pipeline_Simulator Public

   Python 1

5. VLSI_Design_Project VLSI_Design_Project Public

   1

6. Vivado_Scripting_and_Automation Vivado_Scripting_and_Automation Public

   ALEF_Vivado (Automated Library Evaluation Framework) is a tool coded up in Python that automates the synthesis and implementation flow of Xilinx Vivado Tool by running Tcl Scripts for the input Ver…

   Verilog 1