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1. MIPS-50_Instructions_Pipelined_CPU MIPS-50_Instructions_Pipelined_CPU Public

   A 5-level pipelined CPU described with Verilog, supports 50 MIPS instructions and interruption

   Verilog 3 2

2. LowPoly LowPoly Public

   15-618 Final Project: Transforming an image to low poly style

   CMake 14 3

3. cmu-db/noisepage cmu-db/noisepage Public archive

   Self-Driving Database Management System from Carnegie Mellon University

   C++ 1.7k 501

4. BomberManOnline BomberManOnline Public

   Project for Online Game Developing

   JavaScript