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IPCC tweak for WB PAC update
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@David-OConnor
David-OConnor committed Oct 7, 2021
1 parent 2fc88f7 commit d54c7f1
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Showing 4 changed files with 44 additions and 44 deletions.
3 changes: 3 additions & 0 deletions src/clocks/baseline.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -751,6 +751,9 @@ impl Clocks {

rcc.cr.modify(|_, w| {
// Enable bypass mode on HSE, since we're using a ceramic oscillator.
#[cfg(feature = "wl")]
return w.hsebyppwr().bit(self.hse_bypass);
#[cfg(not(feature = "wl"))]
w.hsebyp().bit(self.hse_bypass)
});

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75 changes: 36 additions & 39 deletions src/ipcc.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -360,23 +360,22 @@ impl Ipcc {
// todo currently this is for when processor 1 is transmitting.
match core {
Core::C1 => match channel {
IpccChannel::C1 => self.regs.c1toc2sr.read().ch1f(),
IpccChannel::C2 => self.regs.c1toc2sr.read().ch2f(),
IpccChannel::C3 => self.regs.c1toc2sr.read().ch3f(),
IpccChannel::C4 => self.regs.c1toc2sr.read().ch4f(),
IpccChannel::C5 => self.regs.c1toc2sr.read().ch5f(),
IpccChannel::C6 => self.regs.c1toc2sr.read().ch6f(),
IpccChannel::C1 => self.regs.c1toc2sr.read().ch1f().bit_is_clear(),
IpccChannel::C2 => self.regs.c1toc2sr.read().ch2f().bit_is_clear(),
IpccChannel::C3 => self.regs.c1toc2sr.read().ch3f().bit_is_clear(),
IpccChannel::C4 => self.regs.c1toc2sr.read().ch4f().bit_is_clear(),
IpccChannel::C5 => self.regs.c1toc2sr.read().ch5f().bit_is_clear(),
IpccChannel::C6 => self.regs.c1toc2sr.read().ch6f().bit_is_clear(),
},
Core::C2 => match channel {
IpccChannel::C1 => self.regs.c2toc1sr.read().ch1f(),
IpccChannel::C2 => self.regs.c2toc1sr.read().ch2f(),
IpccChannel::C3 => self.regs.c2toc1sr.read().ch3f(),
IpccChannel::C4 => self.regs.c2toc1sr.read().ch4f(),
IpccChannel::C5 => self.regs.c2toc1sr.read().ch5f(),
IpccChannel::C6 => self.regs.c2toc1sr.read().ch6f(),
IpccChannel::C1 => self.regs.c2toc1sr.read().ch1f().bit_is_clear(),
IpccChannel::C2 => self.regs.c2toc1sr.read().ch2f().bit_is_clear(),
IpccChannel::C3 => self.regs.c2toc1sr.read().ch3f().bit_is_clear(),
IpccChannel::C4 => self.regs.c2toc1sr.read().ch4f().bit_is_clear(),
IpccChannel::C5 => self.regs.c2toc1sr.read().ch5f().bit_is_clear(),
IpccChannel::C6 => self.regs.c2toc1sr.read().ch6f().bit_is_clear(),
},
}
.bit_is_clear()
}

/// Enable a specific type of IPCC interrupt. Note that there isn't an associated `clear_interrupt`
Expand All @@ -403,45 +402,43 @@ impl Ipcc {
pub fn get_rx_channel(&self, core: Core, channel: IpccChannel) -> bool {
match core {
Core::C1 => match channel {
IpccChannel::C1 => self.regs.c1mr.read().ch1om(),
IpccChannel::C2 => self.regs.c1mr.read().ch2om(),
IpccChannel::C3 => self.regs.c1mr.read().ch3om(),
IpccChannel::C4 => self.regs.c1mr.read().ch4om(),
IpccChannel::C5 => self.regs.c1mr.read().ch5om(),
IpccChannel::C6 => self.regs.c1mr.read().ch6om(),
IpccChannel::C1 => self.regs.c1mr.read().ch1om().bit_is_clear(),
IpccChannel::C2 => self.regs.c1mr.read().ch2om().bit_is_clear(),
IpccChannel::C3 => self.regs.c1mr.read().ch3om().bit_is_clear(),
IpccChannel::C4 => self.regs.c1mr.read().ch4om().bit_is_clear(),
IpccChannel::C5 => self.regs.c1mr.read().ch5om().bit_is_clear(),
IpccChannel::C6 => self.regs.c1mr.read().ch6om().bit_is_clear(),
},
Core::C2 => match channel {
IpccChannel::C1 => self.regs.c2mr.read().ch1om(),
IpccChannel::C2 => self.regs.c2mr.read().ch2om(),
IpccChannel::C3 => self.regs.c2mr.read().ch3om(),
IpccChannel::C4 => self.regs.c2mr.read().ch4om(),
IpccChannel::C5 => self.regs.c2mr.read().ch5om(),
IpccChannel::C6 => self.regs.c2mr.read().ch6om(),
IpccChannel::C1 => self.regs.c2mr.read().ch1om().bit_is_clear(),
IpccChannel::C2 => self.regs.c2mr.read().ch2om().bit_is_clear(),
IpccChannel::C3 => self.regs.c2mr.read().ch3om().bit_is_clear(),
IpccChannel::C4 => self.regs.c2mr.read().ch4om().bit_is_clear(),
IpccChannel::C5 => self.regs.c2mr.read().ch5om().bit_is_clear(),
IpccChannel::C6 => self.regs.c2mr.read().ch6om().bit_is_clear(),
},
}
.bit_is_clear()
}

pub fn get_tx_channel(&self, core: Core, channel: IpccChannel) -> bool {
match core {
Core::C1 => match channel {
IpccChannel::C1 => self.regs.c1mr.read().ch1fm(),
IpccChannel::C2 => self.regs.c1mr.read().ch2fm(),
IpccChannel::C3 => self.regs.c1mr.read().ch3fm(),
IpccChannel::C4 => self.regs.c1mr.read().ch4fm(),
IpccChannel::C5 => self.regs.c1mr.read().ch5fm(),
IpccChannel::C6 => self.regs.c1mr.read().ch6fm(),
IpccChannel::C1 => self.regs.c1mr.read().ch1fm().bit_is_clear(),
IpccChannel::C2 => self.regs.c1mr.read().ch2fm().bit_is_clear(),
IpccChannel::C3 => self.regs.c1mr.read().ch3fm().bit_is_clear(),
IpccChannel::C4 => self.regs.c1mr.read().ch4fm().bit_is_clear(),
IpccChannel::C5 => self.regs.c1mr.read().ch5fm().bit_is_clear(),
IpccChannel::C6 => self.regs.c1mr.read().ch6fm().bit_is_clear(),
},
Core::C2 => match channel {
IpccChannel::C1 => self.regs.c2mr.read().ch1fm(),
IpccChannel::C2 => self.regs.c2mr.read().ch2fm(),
IpccChannel::C3 => self.regs.c2mr.read().ch3fm(),
IpccChannel::C4 => self.regs.c2mr.read().ch4fm(),
IpccChannel::C5 => self.regs.c2mr.read().ch5fm(),
IpccChannel::C6 => self.regs.c2mr.read().ch6fm(),
IpccChannel::C1 => self.regs.c2mr.read().ch1fm().bit_is_clear(),
IpccChannel::C2 => self.regs.c2mr.read().ch2fm().bit_is_clear(),
IpccChannel::C3 => self.regs.c2mr.read().ch3fm().bit_is_clear(),
IpccChannel::C4 => self.regs.c2mr.read().ch4fm().bit_is_clear(),
IpccChannel::C5 => self.regs.c2mr.read().ch5fm().bit_is_clear(),
IpccChannel::C6 => self.regs.c2mr.read().ch6fm().bit_is_clear(),
},
}
.bit_is_clear()
}

pub fn set_rx_channel(&mut self, core: Core, channel: IpccChannel, enabled: bool) {
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5 changes: 1 addition & 4 deletions src/usart.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -467,11 +467,8 @@ where
w.addm7().set_bit();
// Set the character to detect
cfg_if! {
if #[cfg(any(feature = "f3", feature = "l4", feature = "h7"))] {
if #[cfg(any(feature = "f3", feature = "l4", feature = "h7", feature = "wl"))] {
w.add().bits(char)
} else if #[cfg(feature = "wl")] {
w.add3_0().bits(char & 0b1111);
w.add7_4().bits(char & (0b1111 << 4))
} else { // todo: Is this right, or backwards?
w.add0_3().bits(char & 0b1111);
w.add4_7().bits(char & (0b1111 << 4))
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5 changes: 4 additions & 1 deletion src/util.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -32,7 +32,7 @@ cfg_if::cfg_if! {
}

cfg_if::cfg_if! {
if #[cfg(any(feature = "l5", feature = "g0"))] {
if #[cfg(any(feature = "l5", feature = "g0", feature = "wl"))] {
use crate::pac::ADC as ADC1;

} else {
Expand Down Expand Up @@ -431,6 +431,9 @@ cfg_if::cfg_if! {
} else {
impl RccPeriph for DAC1 {
fn en_reset(rcc: &RegisterBlock) {
#[cfg(feature = "wl")]
rcc.apb1enr1.modify(|_, w| w.dac1en().set_bit());
#[cfg(not(feature = "wl"))]
rcc_en_reset!(apb1, dac1, rcc);
}
}
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