Skip to content
View DjSPIT's full-sized avatar
😁
😁
Block or Report

Block or report DjSPIT

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
DjSPIT/README.md

Hey There!! I'm DjSPIT πŸ€—

About me

  1. 🧐 I’m interested in Digital and Analog/Mixed Signal VLSI Design, Embedded Systems.
  2. πŸ“– I’m currently learning Computer Vision Applications and Machine Learning
  3. πŸ•΅πŸΌβ€β™‚ Providing an efficient solution for the automated monitoring of autistic and elderly individuals through https://www.autobuddys.in/
  4. πŸ‘οΈ Developing a project in Neuromorphic Systems
  5. 🀝 Open for collaborations
  6. πŸŽ“ Pursuing Final Year, Bachelor of Technology in Electronics Engineering from Sardar Patel Institute of Technology
  7. πŸ€” Always thinking
  8. πŸ‹ You might find me at the gym 🎡 or listening to EDM in my free time.

Experience

  • πŸ‘©πŸ½β€πŸ’» Verilog | C | C++ | Python
  • 🌐 HTML | CSS | ReactJS | Django
  • πŸ“‘ PostgreSQL | mySQL
  • πŸ€– Arduino | Raspberry Pi | Esp8266 | Zybo Z7
  • πŸ“ EagleCAD | Proteus | LTSpice | MATLAB
  • 🧰 Xilinx Vivado | Quartus Prime | Keil uVision | VS code | GitHub

Let's connect!

linkedin  instagram  Mail

Pinned

  1. basic-verilog-codes basic-verilog-codes Public

    These are some of the starter verilog programs which I learned during my Undergraduate Electronics Degree

    Verilog

  2. facer facer Public

    Forked from gjovanov/facer

    Face Recognition in the browser

    Vue

  3. Python-OpenCV Python-OpenCV Public

    This repository contains some of the projects created using Python, OpenCV and MediaPipe Library.

    Python

  4. uart uart Public

    Forked from ben-marshall/uart

    A simple implementation of a UART modem in Verilog.

    Verilog